Visible to Intel only — GUID: hco1416490856260
Ixiasoft
Visible to Intel only — GUID: hco1416490856260
Ixiasoft
1.1.16.4. Maximum Number of QDR II and QDR II+ SRAM Interfaces Supported per FPGA
One interface of ×36 consists of:
- 36 Q pins
- 36 D pins
- 1 K, K# pin pairs
- 1 CQ, CQ# pin pairs
- 19 address pins
- 4 BSWn pins
- WPSn, RPSn
One interface of ×9 consists of:
- 9 Q pins
- 9 D pins
- 1 K, K# pin pairs
- 1 CQ, CQ# pin pairs
- 21 address pins
- 1 BWSn pin
- WPSn, RPSn
Device |
Device Type |
Package Pin Count |
Maximum Number of Interfaces |
---|---|---|---|
Arria II GX |
EP2AGX190 EP2AGX260 |
1,152 |
One ×36 interface and on ×9 interface one each side |
EP2AGX45 EP2AGX65 |
358 |
One ×9 interface on each side No DQ pins on left side |
|
Arria II GZ |
EP2AGZ300 EP2AGZ350 EP2AGZ225 |
1,517 |
|
EP2AGZ300 EP2AGZ350 |
780 |
|
|
Arria V |
5AGXB1 5AGXB3 5AGXB5 5AGXB7 5AGTD3 5AGTD7 |
1,517 |
|
5AGXA1 5AGXA3 |
672 |
|
|
5AGXA5 5AGXA7 |
672 |
|
|
Arria V GZ |
5AGZE5 5AGZE7 |
1,517 |
|
5AGZE1 5AGZE3 |
780 |
|
|
Stratix III |
EP3SL340 |
1,760 |
|
EP3SE50 EP3SL50 EP3SL70 |
484 |
|
|
Stratix IV |
EP4SGX290 EP4SGX360 EP4SGX530 |
1,932 |
|
EP4SE530 EP4SE820 |
1,760 |
||
EP4SGX70 EP4SGX110 EP4SGX180 EP4SGX230 |
780 |
Two ×9 interfaces on each side No DQ pins on right side |
|
Stratix V |
5SGXA5 5SGXA7 |
1,932 |
|
5SGXA3 5SGXA4 |
780 |
|