Visible to Intel only — GUID: hco1416490859725
Ixiasoft
Visible to Intel only — GUID: hco1416490859725
Ixiasoft
1.1.16.6. Maximum Number of LPDDR2 SDRAM Interfaces Supported per FPGA
Each interface of size n, where n is a multiple of 8, consists of:
- n DQ pins (including ECC)
- n/8 DM pins
- n/8 DQS, DQSn pin pairs
- 10 address pins
- 2 command pins (CKE and CSn)
- 1 CK, CK# pin pair up to every three x8 LPDDR2 components
Device |
Device Type |
Package Pin Count |
Maximum Number of LPDDR2 SDRAM Interfaces |
---|---|---|---|
Arria V |
5AGXB1 5AGXB3 5AGXB5 5AGXB7 5AGTD3 5AGTD7 |
1,517 |
|
5AGXA1 5AGXA3 |
672 |
|
|
5AGXA5 5AGXA7 |
672 |
|
|
Cyclone V |
5CGTD9 5CEA9 5CGXC9 |
1,152 |
|
5CEA7 5CGTD7 5CGXC7 |
484 |
|
|
MAX 10 FPGA |
10M50D672 10M40D672 |
762 |
One x16 interface on the right side |
10M50D256 10M40D256 10M25D256 10M16D256 |
256 |
One x16 interface on the right side |
Refer also to the EMIF Device Selector, which is available from the Device Selection option of the External Memory Interfaces IP - Support Center page on the Intel® website.