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Ixiasoft
Visible to Intel only — GUID: hco1416490852004
Ixiasoft
1.1.16.1. Maximum Number of DDR SDRAM Interfaces Supported per FPGA
Each interface of size n, where n is a multiple of 8, consists of:
- n DQ pins (including error correction coding (ECC))
- n/8 DM pins
- n/8 DQS pins
- 18 address pins
- 6 command pins (CAS#, RAS#, WE#, CKE, and CS#)
- 1 CK, CK# pin pair for up to every three ×8 DDR SDRAM components
Device |
Device Type |
Package Pin Count |
Maximum Number of Interfaces |
---|---|---|---|
Arria II GX |
EP2AGX190 EP2AGX260 |
1,152 |
Four ×8 interfaces or one ×72 interface on each side (no DQ pins on left side) |
EP2AGX45 EP2AGX65 |
358 |
|
|
Arria II GZ |
EP2AGZ300 EP2AGZ350 EP2AGZ225 |
1,517 |
Four ×8 interfaces or one ×72 interface on each side |
EP2AGZ300 EP2AGZ350 |
780 |
|
|
Stratix III |
EP3SL340 |
1,760 |
|
EP3SE50 |
484 |
|
|
Stratix IV |
EP4SGX290 EP4SGX360 EP4SGX530 |
1,932 |
or
|
EP4SE530 EP4SE820 |
1,760 |
||
EP4SGX70 EP4SGX110 EP4SGX180 EP4SGX230 |
780 |
|
Refer also to the EMIF Device Selector, which is available from the Device Selection option of the External Memory Interfaces IP - Support Center page on the Intel® website.