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Ixiasoft
4.1.1. LPDDR2 SDRAM Configurations
When using multiple devices, a balanced-T topology is recommended for the signal connected from single point to multiple point, to maintain equal flight time.
You should connect a 200 ohm differential termination resistor between CK/CK# in multiple device designs as shown in the second figure below, to maintain an effective resistance of 100 ohms.
You should also simulate your multiple device design to obtain the optimum drive strength settings and ensure correct operation.
The following figure shows the main signal connections between the FPGA and a single LPDDR2 SDRAM component.
Note to Figure:
- Use external discrete termination, as shown for CKE, but you may require a pull-down resistor to GND. Refer to the LPDDR2 SDRAM device data sheet for more information about LPDDR2 SDRAM power-up sequencing.
The following figure shows the differential resistor placement for CK/CK# for multi-point designs.
Note to Figure:
- Place 200-ohm differential resistors near the memory devices at the end of the last board trace segments.
The following figure shows the detailed balanced topology recommended for the address and command signals in the multi-point design.
Notes to Figure:
- Split the trace close to the memory devices to minimize signal reflections and impedence nonuniformity.
- Keep the TL2 traces as short as possible, so that the memory devices appear as a single load.