Visible to Intel only — GUID: hco1416491091425
Ixiasoft
Visible to Intel only — GUID: hco1416491091425
Ixiasoft
5.7. Layout Approach
You can find timing information under Report DDR in the Timing Analyzer and on the Timing Analysis tab in the parameter editor.
The following flowchart illustrates the recommended process to follow during the board design phase, to determine timing margin and make iterative improvements to your design.
Board Skew
For information on calculating board skew parameters, refer to Board Skew Equations, in this chapter.
The Board Skew Parameter Tool is an interactive tool that can help you calculate board skew parameters if you know the absolute delay values for all the memory related traces.
Memory Timing Parameters
For information on the memory timing parameters to be entered into the parameter editor, refer to the datasheet for your external memory device.