Visible to Intel only — GUID: ysu1505146047708
Ixiasoft
Visible to Intel only — GUID: ysu1505146047708
Ixiasoft
1.1. Interface Pins
The following table lists a summary of the number of pins required for various example memory interfaces. This table uses series OCT with calibration and parallel OCT with calibration, or dynamic calibrated OCT, when applicable, shown by the usage of RUP and RDN pins or RZQ pin.
External Memory Interface |
FPGA DQS Group Size |
# of DQ Pins |
# of DQS/CQ/QK Pins |
# of Control Pins (18) |
# of Address Pins (3) |
# of Command Pins |
# of Clock Pins |
RUP/RDN Pins (4) |
RZQ Pins (11) |
Total Pins (with RUP/RDN pins) |
Total Pins (with RZQ pin) |
---|---|---|---|---|---|---|---|---|---|---|---|
LPDDR2 |
×8 |
8 |
2 |
1 |
10 |
2 |
2 |
N/A |
1 |
N/A |
26 |
16 |
4 |
2 |
10 |
2 |
2 |
N/A |
1 |
N/A |
37 |
||
72 |
18 |
9 |
10 |
2 |
2 |
N/A |
1 |
N/A |
114 |
||
DDR3 SDRAM (5) (6) |
×4 |
4 |
2 |
0 (7) |
14 |
10 |
2 |
2 |
1 |
34 |
33 |
×8 |
8 |
2 |
1 |
14 |
10 |
2 |
2 |
1 |
39 |
38 |
|
16 |
4 |
2 |
14 |
10 |
2 |
2 |
1 |
50 |
49 |
||
DDR2 SDRAM (8) |
×4 |
4 |
1 |
1 (7) |
15 |
9 |
2 |
2 |
1 |
34 |
33 |
×8 |
8 |
1 (9) |
1 |
15 |
9 |
2 |
2 |
1 |
38 |
37 |
|
16 |
2 (9) |
2 |
15 |
9 |
2 |
2 |
1 |
48 |
47 |
||
DDR SDRAM (6) |
×4 |
4 |
1 |
1 (7) |
14 |
7 |
2 |
2 |
1 |
29 |
28 |
×8 |
8 |
1 |
1 |
14 |
7 |
2 |
2 |
1 |
33 |
35 |
|
16 |
2 |
2 |
14 |
7 |
2 |
2 |
1 |
43 |
42 |
||
QDR II+ SRAM (17) |
×18 |
36 |
2 |
2 |
19 |
3 (10) |
2 (14) |
2 |
1 |
66 |
65 |
×36 |
72 |
2 |
4 |
18 |
3 (10) |
2 (14) |
2 |
1 |
103 |
102 |
|
QDR II SRAM |
×9 |
18 |
2 |
1 |
19 |
2 |
4 (15) |
2 |
1 |
48 |
47 |
×18 |
36 |
2 |
2 |
18 |
2 |
4 (15) |
2 |
1 |
66 |
65 |
|
×36 |
72 |
2 |
4 |
17 |
2 |
4 (15) |
2 |
1 |
103 |
102 |
|
RLDRAM 3 CIO (13) |
x9 | 18 | 4 | 2 | 20 | 8 (10) | 6 (16) |
N/A |
1 | N/A |
59 |
36 | 8 | 2 | 19 | 8 (10) | 6 (16) |
N/A |
1 | N/A |
80 | ||
RLDRAM |
×9 |
9 |
2 |
1 |
22 |
7 (10) |
4 (16) |
2 |
1 |
47 |
46 |
18 |
4 |
1 |
21 |
7 (10) |
4 (16) |
2 |
1 |
57 |
56 |
||
×18 |
36 |
4 |
1 |
20 |
7 (10) |
6 (16) |
2 |
1 |
76 |
75 |
|
Notes to table:
|
Intel® devices do not limit the width of external memory interfaces beyond the following requirements:
- Maximum possible interface width in any particular device is limited by the number of DQS groups available.
- Sufficient clock networks are available to the interface PLL as required by the IP.
- Sufficient spare pins exist within the chosen bank or side of the device to include all other address and command, and clock pin placement requirements.
- The greater the number of banks, the greater the skew, hence Intel® recommends that you always generate a test project of your desired configuration and confirm that it meets timing.
Section Content
Estimating Pin Requirements
DDR, DDR2, and DDR3 SDRAM Clock Signals
DDR, DDR2, and DDR3 SDRAM Command and Address Signals
DDR, DDR2, and DDR3 SDRAM Data, Data Strobes, DM/DBI, and Optional ECC Signals
DDR, DDR2, and DDR3 SDRAM DIMM Options
QDR II and QDR II+ SRAM Clock Signals
QDR II and QDR II+ SRAM Command Signals
QDR II and QDR II+ SRAM Address Signals
QDR II and QDR II+ SRAM Data, BWS, and QVLD Signals
RLDRAM II and RLDRAM 3 Clock Signals
RLDRAM II and RLDRAM 3 Commands and Addresses
RLDRAM II and RLDRAM 3 Data, DM and QVLD Signals
LPDDR2 Clock Signal
LPDDR2 Command and Address Signal
LPDDR2 Data, Data Strobe, and DM Signals
Maximum Number of Interfaces
OCT Support