External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

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ID 683385
Date 3/06/2023
Public
Document Table of Contents
Document Table of Contents x
1. Planning Pin and FPGA Resources 2. DDR2 and DDR3 SDRAM Board Design Guidelines 3. Dual-DIMM DDR2 and DDR3 SDRAM Board Design Guidelines 4. LPDDR2 SDRAM Board Design Guidelines 5. RLDRAM II and RLDRAM 3 Board Design Guidelines 6. QDR II/II+ SRAM Board Design Guidelines 7. Implementing and Parameterizing Memory IP 8. Simulating Memory IP 9. Analyzing Timing of Memory IP 10. Debugging Memory IP 11. Optimizing the Controller 12. PHY Considerations 13. Power Estimation Methods for External Memory Interfaces
1. Planning Pin and FPGA Resources x
1.1. Interface Pins 1.2. Guidelines for UniPHY-based External Memory Interface IP 1.3. Using PLL Guidelines 1.4. PLL Cascading 1.5. DLL 1.6. Other FPGA Resources 1.7. Document Revision History
1.1. Interface Pins x
1.1.1. Estimating Pin Requirements 1.1.2. DDR, DDR2, and DDR3 SDRAM Clock Signals 1.1.3. DDR, DDR2, and DDR3 SDRAM Command and Address Signals 1.1.4. DDR, DDR2, and DDR3 SDRAM Data, Data Strobes, DM/DBI, and Optional ECC Signals 1.1.5. DDR, DDR2, and DDR3 SDRAM DIMM Options 1.1.6. QDR II and QDR II+ SRAM Clock Signals 1.1.7. QDR II and QDR II+ SRAM Command Signals 1.1.8. QDR II and QDR II+ SRAM Address Signals 1.1.9. QDR II and QDR II+ SRAM Data, BWS, and QVLD Signals 1.1.10. RLDRAM II and RLDRAM 3 Clock Signals 1.1.11. RLDRAM II and RLDRAM 3 Commands and Addresses 1.1.12. RLDRAM II and RLDRAM 3 Data, DM and QVLD Signals 1.1.13. LPDDR2 Clock Signal 1.1.14. LPDDR2 Command and Address Signal 1.1.15. LPDDR2 Data, Data Strobe, and DM Signals 1.1.16. Maximum Number of Interfaces 1.1.17. OCT Support
1.1.16. Maximum Number of Interfaces x
1.1.16.1. Maximum Number of DDR SDRAM Interfaces Supported per FPGA 1.1.16.2. Maximum Number of DDR2 SDRAM Interfaces Supported per FPGA 1.1.16.3. Maximum Number of DDR3 SDRAM Interfaces Supported per FPGA 1.1.16.4. Maximum Number of QDR II and QDR II+ SRAM Interfaces Supported per FPGA 1.1.16.5. Maximum Number of RLDRAM II Interfaces Supported per FPGA 1.1.16.6. Maximum Number of LPDDR2 SDRAM Interfaces Supported per FPGA
1.2. Guidelines for UniPHY-based External Memory Interface IP x
1.2.1. General Pin-out Guidelines for UniPHY-based External Memory Interface IP 1.2.2. Pin-out Rule Exceptions for ×36 Emulated QDR II and QDR II+ SRAM Interfaces in Arria II, Stratix III and Stratix IV Devices 1.2.3. Pin-out Rule Exceptions for RLDRAM II and RLDRAM 3 Interfaces 1.2.4. Pin-out Rule Exceptions for QDR II and QDR II+ SRAM Burst-length-of-two Interfaces 1.2.5. Pin Connection Guidelines Tables 1.2.6. PLLs and Clock Networks
1.2.2. Pin-out Rule Exceptions for ×36 Emulated QDR II and QDR II+ SRAM Interfaces in Arria II, Stratix III and Stratix IV Devices x
1.2.2.1. Timing Impact on x36 Emulation 1.2.2.2. Rules to Combine Groups 1.2.2.3. Determining the CQ/CQn Arrival Time Skew
1.2.3. Pin-out Rule Exceptions for RLDRAM II and RLDRAM 3 Interfaces x
1.2.3.1. Interfacing with ×9 RLDRAM II CIO Devices 1.2.3.2. Interfacing with ×18 RLDRAM II and RLDRAM 3 CIO Devices 1.2.3.3. Interfacing with RLDRAM II and RLDRAM 3 ×36 CIO Devices
1.2.5. Pin Connection Guidelines Tables x
1.2.5.1. DDR3 SDRAM With Leveling Interface Pin Utilization Applicable for Arria V GZ, Stratix III, Stratix IV, and Stratix V Devices 1.2.5.2. QDR II and QDR II+ SRAM Pin Utilization for Arria II, Arria V, Stratix III, Stratix IV, and Stratix V Devices 1.2.5.3. RLDRAM II CIO Pin Utilization for Arria II GZ, Arria V, Stratix III, Stratix IV, and Stratix V Devices  1.2.5.4. LPDDR2 Pin Utilization for Arria V, Cyclone V, and MAX 10 FPGA Devices 1.2.5.5. Additional Guidelines for Arria V GZ and Stratix V Devices 1.2.5.6. Additional Guidelines for Arria V ( Except Arria V GZ) Devices 1.2.5.7. Additional Guidelines for MAX 10 Devices 1.2.5.8. Additional Guidelines for Cyclone V Devices
1.2.6. PLLs and Clock Networks x
1.2.6.1. Number of PLLs Available in Intel® Device Families 1.2.6.2. Number of Enhanced PLL Clock Outputs and Dedicated Clock Outputs Available in Intel® Device Families 1.2.6.3. Number of Clock Networks Available in Intel® Device Families 1.2.6.4. Clock Network Usage in UniPHY-based Memory Interfaces—DDR2 and DDR3 SDRAM (1) (2) 1.2.6.5. Clock Network Usage in UniPHY-based Memory Interfaces—RLDRAM II, and QDR II and QDR II+ SRAM 1.2.6.6. PLL Usage for DDR, DDR2, and DDR3 SDRAM Without Leveling Interfaces 1.2.6.7. PLL Usage for DDR3 SDRAM With Leveling Interfaces
2. DDR2 and DDR3 SDRAM Board Design Guidelines x
2.1. Leveling and Dynamic Termination 2.2. DDR2 Terminations and Guidelines 2.3. DDR3 Terminations in Arria V, Cyclone V, Stratix III, Stratix IV, and Stratix V 2.4. Layout Approach 2.5. Channel Signal Integrity Measurement 2.6. Design Layout Guidelines 2.7. Package Deskew 2.8. Document Revision History
2.1. Leveling and Dynamic Termination x
2.1.1. Read and Write Leveling 2.1.2. Dynamic ODT 2.1.3. Dynamic On-Chip Termination 2.1.4. Dynamic On-Chip Termination in Stratix III and Stratix IV Devices 2.1.5. Dynamic OCT in Stratix V Devices
2.1.3. Dynamic On-Chip Termination x
2.1.3.1. FPGA Writing to Memory 2.1.3.2. FPGA Reading from Memory
2.2. DDR2 Terminations and Guidelines x
2.2.1. Termination for DDR2 SDRAM 2.2.2. DDR2 Design Layout Guidelines 2.2.3. General Layout Guidelines 2.2.4. Layout Guidelines for DDR2 SDRAM Interface
2.2.1. Termination for DDR2 SDRAM x
2.2.1.1. External Parallel Termination 2.2.1.2. On-Chip Termination 2.2.1.3. Recommended Termination Schemes
2.3. DDR3 Terminations in Arria V, Cyclone V, Stratix III, Stratix IV, and Stratix V x
2.3.1. Terminations for Single-Rank DDR3 SDRAM Unbuffered DIMM 2.3.2. Terminations for Multi-Rank DDR3 SDRAM Unbuffered DIMM 2.3.3. Terminations for DDR3 SDRAM Registered DIMM 2.3.4. Terminations for DDR3 SDRAM Load-Reduced DIMM 2.3.5. Terminations for DDR3 SDRAM Components With Leveling
2.3.5. Terminations for DDR3 SDRAM Components With Leveling x
2.3.5.1. DDR3 SDRAM Components With or Without Leveling
2.5. Channel Signal Integrity Measurement x
2.5.1. Importance of Accurate Channel Signal Integrity Information 2.5.2. Understanding Channel Signal Integrity Measurement 2.5.3. How to Enter Calculated Channel Signal Integrity Values 2.5.4. Guidelines for Calculating DDR3 Channel Signal Integrity
2.6. Design Layout Guidelines x
2.6.1. General Layout Guidelines 2.6.2. Layout Guidelines for DDR3 SDRAM Interfaces 2.6.3. Length Matching Rules 2.6.4. Spacing Guidelines 2.6.5. Layout Guidelines for DDR3 SDRAM Wide Interface (>72 bits)
2.6.5. Layout Guidelines for DDR3 SDRAM Wide Interface (>72 bits) x
2.6.5.1. Fly-By Network Design for Clock, Command, and Address Signals
2.7. Package Deskew x
2.7.1. Package Deskew Recommendation for Stratix V Devices 2.7.2. DQ/DQS/DM Deskew 2.7.3. Address and Command Deskew 2.7.4. Deskew Example 2.7.5. Package Migration 2.7.6. Package Deskew for RLDRAM II and RLDRAM 3
3. Dual-DIMM DDR2 and DDR3 SDRAM Board Design Guidelines x
3.1. General Layout Guidelines 3.2. Dual-Slot Unbuffered DDR2 SDRAM 3.3. Dual-Slot Unbuffered DDR3 SDRAM 3.4. Document Revision History
3.2. Dual-Slot Unbuffered DDR2 SDRAM x
3.2.1. Overview of ODT Control 3.2.2. DIMM Configuration 3.2.3. Dual-DIMM Memory Interface with Slot 1 Populated 3.2.4. Dual-DIMM with Slot 2 Populated 3.2.5. Dual-DIMM Memory Interface with Both Slot 1 and Slot 2 Populated 3.2.6. Dual-DIMM DDR2 Clock, Address, and Command Termination and Topology 3.2.7. Control Group Signals 3.2.8. Clock Group Signals
3.2.3. Dual-DIMM Memory Interface with Slot 1 Populated x
3.2.3.1. FPGA Writing to Memory 3.2.3.2. Write to Memory Using an ODT Setting of 150-ohm 3.2.3.3. Reading from Memory
3.2.4. Dual-DIMM with Slot 2 Populated x
3.2.4.1. FPGA Writing to Memory 3.2.4.2. Write to Memory Using an ODT Setting of 150-ohm 3.2.4.3. Reading from Memory
3.2.5. Dual-DIMM Memory Interface with Both Slot 1 and Slot 2 Populated x
3.2.5.1. FPGA Writing to Memory 3.2.5.2. Write to Memory in Slot 1 Using an ODT Setting of 75-ohm 3.2.5.3. Reading From Memory
3.3. Dual-Slot Unbuffered DDR3 SDRAM x
3.3.1. Comparison of DDR3 and DDR2 DQ and DQS ODT Features and Topology 3.3.2. Dual-DIMM DDR3 Clock, Address, and Command Termination and Topology 3.3.3. FPGA OCT Features
3.3.2. Dual-DIMM DDR3 Clock, Address, and Command Termination and Topology x
3.3.2.1. Address and Command Signals 3.3.2.2. Control Group Signals 3.3.2.3. Clock Group Signals
3.3.3. FPGA OCT Features x
3.3.3.1. Arria V, Cyclone V, Stratix III, Stratix IV, and Stratix V Devices 3.3.3.2. Arria II GX Devices
4. LPDDR2 SDRAM Board Design Guidelines x
4.1. LPDDR2 Guidance 4.2. Document Revision History
4.1. LPDDR2 Guidance x
4.1.1. LPDDR2 SDRAM Configurations 4.1.2. OCT Signal Terminations for Arria V and Cyclone V Devices 4.1.3. General Layout Guidelines 4.1.4. LPDDR2 Layout Guidelines
4.1.2. OCT Signal Terminations for Arria V and Cyclone V Devices x
4.1.2.1. Outputs from the FPGA to the LPDDR2 Component 4.1.2.2. Input to the FPGA from the LPDDR2 SDRAM Component 4.1.2.3. Termination Schemes
5. RLDRAM II and RLDRAM 3 Board Design Guidelines x
5.1. RLDRAM II Configurations 5.2. RLDRAM 3 Configurations 5.3. Signal Terminations 5.4. PCB Layout Guidelines 5.5. General Layout Guidelines 5.6. RLDRAM II and RLDRAM 3 Layout Guidelines 5.7. Layout Approach 5.8. Package Deskew for RLDRAM II and RLDRAM 3 5.9. Document Revision History
5.3. Signal Terminations x
5.3.1. Input to the FPGA from the RLDRAM Components 5.3.2. Outputs from the FPGA to the RLDRAM II and RLDRAM 3 Components 5.3.3. RLDRAM II Termination Schemes 5.3.4. RLDRAM 3 Termination Schemes
5.7. Layout Approach x
5.7.1. Arria V and Stratix V Board Setting Parameters
6. QDR II/II+ SRAM Board Design Guidelines x
6.1. QDR II SRAM Configurations 6.2. Signal Terminations 6.3. General Layout Guidelines 6.4. QDR II Layout Guidelines 6.5. QDR II SRAM Layout Approach 6.6. Package Deskew for QDR II 6.7. Document Revision History
6.2. Signal Terminations x
6.2.1. Output from the FPGA to the QDR II SRAM Component 6.2.2. Input to the FPGA from the QDR II SRAM Component 6.2.3. Termination Schemes
7. Implementing and Parameterizing Memory IP x
7.1. Design Flow 7.2. UniPHY-Based External Memory Interface IP 7.3. Document Revision History
7.1. Design Flow x
7.1.1. IP Catalog Design Flow 7.1.2. Platform Designer System Integration Tool Design Flow
7.1.1. IP Catalog Design Flow x
7.1.1.1. IP Catalog and Parameter Editor 7.1.1.2. Specifying Parameters for the IP Catalog Flow 7.1.1.3. Using Example Designs 7.1.1.4. Constraining the Design 7.1.1.5. Compiling the Design
7.1.1.4. Constraining the Design x
7.1.1.4.1. Adding Pins and DQ Group Assignments
7.1.2. Platform Designer System Integration Tool Design Flow x
7.1.2.1. Specify Parameters for the Platform Designer Flow 7.1.2.2. Completing the Platform Designer System
7.2. UniPHY-Based External Memory Interface IP x
7.2.1. Platform Designer Interfaces 7.2.2. Generated Files for Memory Controllers with the UniPHY IP 7.2.3. Parameterizing Memory Controllers 7.2.4. Board Settings 7.2.5. Controller Settings for UniPHY IP 7.2.6. Diagnostics for UniPHY IP
7.2.1. Platform Designer Interfaces x
7.2.1.1. DDR2 SDRAM Controller with UniPHY Intel FPGA IP Interfaces 7.2.1.2. DDR3 SDRAM Controller with UniPHY Intel FPGA IP Interfaces 7.2.1.3. LPDDR2 SDRAM Controller with UniPHY Intel FPGA IP Interfaces 7.2.1.4. QDR II and QDR II+ SRAM Controller with UniPHY Intel FPGA IP Interfaces 7.2.1.5. RLDRAM II Controller with UniPHY Intel FPGA IP Interfaces 7.2.1.6. RLDRAM 3 UniPHY Intel FPGA IP Interface
7.2.3. Parameterizing Memory Controllers x
7.2.3.1. PHY Settings for UniPHY IP 7.2.3.2. Memory Parameters for LPDDR2, DDR2 and DDR3 SDRAM Controller with UniPHY Intel FPGA IP 7.2.3.3. Memory Parameters for QDR II and QDR II+ SRAM Controller with UniPHY Intel FPGA IP 7.2.3.4. Memory Parameters for RLDRAM II Controller with UniPHY Intel FPGA IP 7.2.3.5. Memory Timing Parameters for DDR2, DDR3, and LPDDR2 SDRAM Controller with UniPHY Intel FPGA IP 7.2.3.6. Memory Timing Parameters for QDR II and QDR II+ SRAM Controller with UniPHY Intel FPGA IP 7.2.3.7. Memory Timing Parameters for RLDRAM II Controller with UniPHY Intel FPGA IP 7.2.3.8. Memory Parameters for RLDRAM 3 UniPHY Intel FPGA IP
7.2.3.2. Memory Parameters for LPDDR2, DDR2 and DDR3 SDRAM Controller with UniPHY Intel FPGA IP x
7.2.3.2.1. Memory Initialization Options for DDR2 7.2.3.2.2. Memory Initialization Options for DDR3 7.2.3.2.3. Memory Initialization Options for LPDDR2
7.2.4. Board Settings x
7.2.4.1. Setup and Hold Derating for UniPHY IP 7.2.4.2. Intersymbol Interference Channel Signal Integrity for UniPHY IP 7.2.4.3. Board Skews for UniPHY IP
7.2.4.3. Board Skews for UniPHY IP x
7.2.4.3.1. Board Skew Parameters for LPDDR2/DDR2/DDR3 SDRAM 7.2.4.3.2. Board Skew Parameters for QDR II and QDR II+ 7.2.4.3.3. Board Skew parameters for RLDRAM II and RLDRAM 3
8. Simulating Memory IP x
8.1. Simulation Options 8.2. Simulation Walkthrough with UniPHY IP 8.3. Document Revision History
8.2. Simulation Walkthrough with UniPHY IP x
8.2.1. Simulation Scripts 8.2.2. Preparing the Vendor Memory Model 8.2.3. Functional Simulation with Verilog HDL 8.2.4. Functional Simulation with VHDL 8.2.5. Simulating the Example Design 8.2.6. UniPHY Abstract PHY Simulation 8.2.7. PHY-Only Simulation 8.2.8. Post-fit Functional Simulation 8.2.9. Simulation Issues
8.2.8. Post-fit Functional Simulation x
8.2.8.1. Running Post-fit Simulation
9. Analyzing Timing of Memory IP x
9.1. Memory Interface Timing Components 9.2. FPGA Timing Paths 9.3. Timing Constraint and Report Files for UniPHY IP 9.4. Timing Analysis Description 9.5. Timing Report DDR 9.6. Report SDC 9.7. Calibration Effect in Timing Analysis 9.8. Timing Model Assumptions and Design Rules 9.9. Common Timing Closure Issues 9.10. Optimizing Timing 9.11. Timing Deration Methodology for Multiple Chip Select DDR2 and DDR3 SDRAM Designs 9.12. Performing I/O Timing Analysis 9.13. Document Revision History
9.1. Memory Interface Timing Components x
9.1.1. Source-Synchronous Paths 9.1.2. Calibrated Paths 9.1.3. Internal FPGA Timing Paths 9.1.4. Other FPGA Timing Parameters
9.2. FPGA Timing Paths x
9.2.1. Arria II Device PHY Timing Paths 9.2.2. Stratix III and Stratix IV PHY Timing Paths 9.2.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Timing paths
9.4. Timing Analysis Description x
9.4.1. UniPHY IP Timing Analysis
9.4.1. UniPHY IP Timing Analysis x
9.4.1.1. Address and Command 9.4.1.2. PHY or Core 9.4.1.3. PHY or Core Reset 9.4.1.4. Read Capture and Write 9.4.1.5. Read Resynchronization 9.4.1.6. DQS versus CK—Arria II GX and Cyclone IV Devices 9.4.1.7. Write Leveling tDQSS 9.4.1.8. Write Leveling tDSH/tDSS 9.4.1.9. DK versus CK (RLDRAM II with UniPHY) 9.4.1.10. Bus Turnaround Time
9.4.1.4. Read Capture and Write x
9.4.1.4.1. Stratix III 9.4.1.4.2. Arria II, Arria V, Cyclone V, Stratix IV and Stratix V
9.7. Calibration Effect in Timing Analysis x
9.7.1. Calibration Emulation for Calibrated Path 9.7.2. Calibration Error or Quantization Error 9.7.3. Calibration Uncertainties 9.7.4. Memory Calibration
9.8. Timing Model Assumptions and Design Rules x
9.8.1. Memory Clock Output Assumptions 9.8.2. Write Data Assumptions 9.8.3. Read Data Assumptions 9.8.4. DLL Assumptions 9.8.5. PLL and Clock Network Assumptions for Stratix III Devices
9.8.1. Memory Clock Output Assumptions x
9.8.1.1. Memory Clock Assumptions for Stratix III Devices
9.8.2. Write Data Assumptions x
9.8.2.1. Write Data Assumptions for Stratix III Devices
9.8.3. Read Data Assumptions x
9.8.3.1. Read Data Assumptions for Stratix III Devices
9.9. Common Timing Closure Issues x
9.9.1. Missing Timing Margin Report 9.9.2. Incomplete Timing Margin Report 9.9.3. Read Capture Timing 9.9.4. Write Timing 9.9.5. Address and Command Timing 9.9.6. PHY Reset Recovery and Removal 9.9.7. Clock-to-Strobe (for DDR and DDR2 SDRAM Only) 9.9.8. Read Resynchronization and Write Leveling Timing (for SDRAM Only)
9.11. Timing Deration Methodology for Multiple Chip Select DDR2 and DDR3 SDRAM Designs x
9.11.1. Multiple Chip Select Configuration Effects 9.11.2. Timing Deration using the Board Settings
9.11.1. Multiple Chip Select Configuration Effects x
9.11.1.1. ISI Effects 9.11.1.2. Calibration Effects 9.11.1.3. Board Effects
9.11.2. Timing Deration using the Board Settings x
9.11.2.1. Slew Rates 9.11.2.2. Slew Rate Setup, Hold, and Derating Calculation 9.11.2.3. Intersymbol Interference 9.11.2.4. Measuring Eye Reduction for Address/Command, DQ, and DQS Setup and Hold Time
9.12. Performing I/O Timing Analysis x
9.12.1. Performing I/O Timing Analysis with Third-Party Simulation Tools 9.12.2. Performing Advanced I/O Timing Analysis with Board Trace Delay Model
10. Debugging Memory IP x
10.1. Resource and Planning Issues 10.2. Interface Configuration Performance Issues 10.3. Functional Issue Evaluation 10.4. Timing Issue Characteristics 10.5. Verifying Memory IP Using the Signal Tap II Logic Analyzer 10.6. Hardware Debugging Guidelines 10.7. Categorizing Hardware Issues 10.8. EMIF Debug Toolkit Overview 10.9. Document Revision History
10.1. Resource and Planning Issues x
10.1.1. Dedicated DLL Resources 10.1.2. Dedicated IOE DQS Group Resources and Pins 10.1.3. Specific PLL Resources 10.1.4. Specific Global, Regional and Dual-Regional Clock Net Resources 10.1.5. Planning Your Design 10.1.6. Optimizing Design Utilization
10.2. Interface Configuration Performance Issues x
10.2.1. Interface Configuration Bottleneck and Efficiency Issues
10.3. Functional Issue Evaluation x
10.3.1. Correct Combination of the Quartus Prime Software and ModelSim* - Intel® FPGA Edition Device Models 10.3.2. Intel® IP Memory Model 10.3.3. Vendor Memory Model 10.3.4. Insufficient Memory in Your PC 10.3.5. Transcript Window Messages 10.3.6. Passing Simulation 10.3.7. Modifying the Example Driver to Replicate the Failure
10.4. Timing Issue Characteristics x
10.4.1. Evaluating FPGA Timing Issues 10.4.2. Evaluating External Memory Interface Timing Issues
10.5. Verifying Memory IP Using the Signal Tap II Logic Analyzer x
10.5.1. Signals to Monitor with the Signal Tap II Logic Analyzer
10.6. Hardware Debugging Guidelines x
10.6.1. Create a Simplified Design that Demonstrates the Same Issue 10.6.2. Measure Power Distribution Network 10.6.3. Measure Signal Integrity and Setup and Hold Margin 10.6.4. Vary Voltage 10.6.5. Use Freezer Spray and Heat Gun 10.6.6. Operate at a Lower Speed 10.6.7. Determine Whether the Issue Exists in Previous Versions of Software 10.6.8. Determine Whether the Issue Exists in the Current Version of Software 10.6.9. Try A Different PCB 10.6.10. Try Other Configurations 10.6.11. Debugging Checklist
10.7. Categorizing Hardware Issues x
10.7.1. Signal Integrity Issues 10.7.2. Hardware and Calibration Issues
10.7.1. Signal Integrity Issues x
10.7.1.1. Characteristics of Signal Integrity Issues 10.7.1.2. Evaluating SignaI Integrity Issues
10.7.1.2. Evaluating SignaI Integrity Issues x
10.7.1.2.1. Skew 10.7.1.2.2. Crosstalk 10.7.1.2.3. Power System 10.7.1.2.4. Clock Signals 10.7.1.2.5. Read Data Valid Window and Eye Diagram 10.7.1.2.6. Write Data Valid Window and Eye Diagram 10.7.1.2.7. OCT and ODT Usage
10.7.2. Hardware and Calibration Issues x
10.7.2.1. Evaluating Hardware and Calibration Issues
10.7.2.1. Evaluating Hardware and Calibration Issues x
10.7.2.1.1. Write Timing Margin 10.7.2.1.2. Read Timing Margin 10.7.2.1.3. Address and Command Timing Margin 10.7.2.1.4. Resynchronization Timing Margin 10.7.2.1.5. Postamble Timing Issues and Margin 10.7.2.1.6. Intermittent Issue Evaluation
11. Optimizing the Controller x
11.1. Factors Affecting Efficiency 11.2. Ways to Improve Efficiency 11.3. Document Revision History
11.1. Factors Affecting Efficiency x
11.1.1. Interface Standard 11.1.2. Bank Management Efficiency 11.1.3. Data Transfer
11.2. Ways to Improve Efficiency x
11.2.1. DDR2 SDRAM Controller 11.2.2. Auto-Precharge Commands 11.2.3. Additive Latency 11.2.4. Bank Interleaving 11.2.5. Command Queue Look-Ahead Depth 11.2.6. Additive Latency and Bank Interleaving 11.2.7. User-Controlled Refresh 11.2.8. Frequency of Operation 11.2.9. Burst Length 11.2.10. Series of Reads or Writes 11.2.11. Data Reordering 11.2.12. Starvation Control 11.2.13. Command Reordering 11.2.14. Bandwidth 11.2.15. Efficiency Monitor
12. PHY Considerations x
12.1. Core Logic and User Interface Data Rate 12.2. Hard and Soft Memory PHY 12.3. Sequencer 12.4. PLL, DLL and OCT Resource Sharing 12.5. Pin Placement Consideration 12.6. Document Revision History
13. Power Estimation Methods for External Memory Interfaces x
13.1. Performing Vector-Based Power Analysis with the Power Analyzer 13.2. Document Revision History
1. Planning Pin and FPGA Resources
2. DDR2 and DDR3 SDRAM Board Design Guidelines
3. Dual-DIMM DDR2 and DDR3 SDRAM Board Design Guidelines
4. LPDDR2 SDRAM Board Design Guidelines
5. RLDRAM II and RLDRAM 3 Board Design Guidelines
6. QDR II/II+ SRAM Board Design Guidelines
7. Implementing and Parameterizing Memory IP
8. Simulating Memory IP
9. Analyzing Timing of Memory IP
10. Debugging Memory IP
11. Optimizing the Controller
12. PHY Considerations
13. Power Estimation Methods for External Memory Interfaces

7.3. Document Revision History

Date Version Changes
March 2023 2023.03.06 Removed all Intel® Arria® 10 and Intel® Stratix® 10-related content.
May 2017 2017.05.08
  • Added Stratix 10 External Memory Interface IP section.
  • Rebranded as Intel.
October 2016 2016.10.31
  • Updated Generated Directory Structure and Key Files for Example Simulation Designs and Generated Directory Structure and Key Files for Example Synthesis Designs tables.
  • Removed Parameterizing Arria 10 External Memory Interface IP section.
  • Added protocol-specific parameter sections for Arria 10 EMIF IP.
  • Added Equations for Arria 10 EMIF IP Board Skew Parameters section.
May 2016 2016.05.02
  • Modified window duration in descriptions of tDQSCK Delta Medium and tDQSCK Delta Long in the Parameter Descriptions table in Memory Timing Parameters for DDR2, DDR3, and LPDDR2 SDRAM for UniPHY IP.
  • Modified description of Enable the Efficiency Monitor and Protocol Checker on the Controller Avalon Interface in the Simulation Options table in Diagnostics for UniPHY IP.
  • Removed cal_debug_burstcount from Interface: cal_debug_avalon_slave table in Qsys Interfaces.
  • Modified Direction information for entries in Interface: cal_debug_out_avalon_master table in Qsys Interfaces.
  • Removed two rows from the Generated Directory Structure and Key Files for Simulation table in Generated Files for Arria 10 External Memory Interface IP.
  • Replaced Generated Directory Structure and Key Files for Example Designs table with Generated Directory Structure and Key Files for Example Simulation Designs and Generated Directory Structure and Key Files for Example Synthesis Designs tables in Generated Files for Arria 10 External Memory Interface IP.
  • Added entry for Slew rate to Group: I/O / Address/Command and Group: I/O / Memory Clock tables in I/O Parameters for Arria 10 EMIF IP.
  • Modified description of DDR3 LRDIMM additional control words entry in Group: Memory Topology / Mode Register Settings table in Memory Topology Parameters for Arria 10 EMIF IP.
  • Modified supported protocol information for Enable Error Detection and Correction Logic and Enable Auto Error Correction entries in Group: Controller / Configuration, Status and Error Handling table in Controller Parameters for Arria 10 EMIF IP.
  • Minor change to description of Calibration mode in Group: Diagnostic / Simulation Options table in Diagnostic Parameters for Arria 10 EMIF IP.
  • Added QDR-IV to supported protocols for Skip VREF calibration in Group: Diagnostic / Calibration Debug Options table in Diagnostic Parameters for Arria 10 EMIF IP.
  • Added Calibration address 0, Calibration address 1, and Enable automatic calibration after reset to Group: Diagnostic / Calibration Debug Options table in Diagnostic Parameters for Arria 10 EMIF IP.
  • Added Group: Diagnostic / Traffic Generator table to Diagnostic Parameters for Arria 10 EMIF IP. Moved some entries from Group: Diagnostic / Example Design table to new Group: Diagnostic / Traffic Generator table.
November 2015 2015.11.02
  • Added note to descriptions of Minimum delay difference between CK and DQS and Maximum delay difference between CK and DQS in Board Skew parameters for LPDDR2/DDR2/DDR3 SDRAM.
  • Added text to description of Maximum skew between DQS groups in Board Skew parameters for LPDDR2/DDR2/DDR3 SDRAM.
  • Changed description of emif_usr_clk in the Interface: emif_usr_clk_clock_source table in Qsys Interfaces.
  • Changed description of emif_usr_reset_n in the Interface: emif_usr_reset_reset_source table in Qsys Interfaces.
  • Added Interface: emif_usr_clk_sec_clock_source and Interface: emif_usr_reset_sec_reset_source tables in Qsys Interfaces.
  • Added several options to the Simulation Options, Calibration Debug Options, and Example Design tables in Diagnostic Parameters for Arria 10 EMIF IP.
  • Changed instances of Quartus II to Quartus Prime.
  • Added LPDDR3
  • Removed Use address parity bit parameter for QDR IV
  • Removed following DDR4 parameters:
    • Write CRC enable
    • DDR4 geardown mode
    • Per-DRAM addressability
    • Temperature sensor readout
    • Write CMD latency for CRC/DM enable
    • MPR read format
    • CS to Addr/CMD Latency
    • Enable DM pins
    • Addr/CMD persistent error
    • Write DBI
    • Read DBI
  • Removed group board timing/slew rates table
  • Removed Maximum system skew within QK group parameters for RLDRAM 3
  • Removed Maximum system skew within Q group and Maximum skew within D group parameters
May 2015 2015.05.04 Added information to the Description column for the cal_debug_avalon_slave, cal_debug_clk_clock_sink, and cal_debug_out_reset_reset_source tables in the Qsys Interfaces topic.
December 2014 2014.12.15
  • Added MAX 10 device support to the PHY Parameters table in PHY Settings for UniPHY IP
  • Changed Memory Parameters for LPDDR2, DDR2, and DDR3 SDRAM table to accommodate MAX 10 devices.
  • Added Enable Deep Power-Down Controls parameter to Controller Settings table in Controller Settings for UniPHY IP section.
  • Arria 10 External Memory Interface IP section:
    • Removed references to Arria 10 devices from Board Settings topic in UniPHY-Based External Memory Interface IP section. Added new Board Timing topic.
    • Added QDR IV support to tables in Qsys Interfaces section.
    • Removed afi_c from afi_conduit_end table and mem_c from mem_conduit_end table.
    • Changed description of global_reset_n signal in the Interface: global_reset_reset_sink table.
    • Added Board Timing section and subtopics.
  • Changed Memory Initialization Options for DDR3 table to accommodate MAX 10 devices.
  • Replaced Parameter Descriptions table in Memory Timing Parameters for DDR2, DDR3, and LPDDR2 SDRAM for UniPHY IP section with new table including LPDDR2.
  • Removed General Settings for Arria 10 EMIF IP section.
  • Parameterizing Arria 10 External Memory Interface IP section:
    • Added DDR4 support to tables.
    • Changed descriptions of RDIMM/LRDIMM control words and LRDIMM additional control words in Group: Memory Topology / Mode Register Settings table.
    • Removed Chip ID Width from Group: Memory Topology / Topology table.
    • Added entry for Instantiate two controllers sharing a Ping Pong PHY, and expanded description of Configuration, in the Group: General / Interface table.
    • Changed Total interface width entry to DQ width and changed Place ALERT# pin to ALERT# pin placement in Group: Memory Topology / Topology table.
August 2014 2014.08.15
  • Added notes about Arria 10 EMIF IP to beginning of chapter.
  • Added IP Catalog to Design Flows figure.
  • Replaced MegaWizard Plug-In Manager Flow with IP Catalog Design Flow.
  • Revised Specify Parameters for the Qsys Flow and Completing the Qsys System sections.
  • Added information to description of mem_doff_n in QDR II and QDR II+ SRAM Controller with UniPHY Interfaces table.
  • Reorganized into separate sections for UniPHY-Based External Memory Interfaces and Arria 10 External Memory Interface IP.
  • Replaced the following sections with the new Arria 10 EMIF IP Interfaces section:
    • DDR3 Controller with Arria 10 EMIF Interfaces
    • LPDDR2 SDRAM Controller with Arria 10 EMIF Interfaces
    • QDR II/II+ Controller with Arria 10 EMIF Interfaces
    • RLDRAM II Controller with Arria 10 EMIF Interfaces
    • RLDRAM 3 Controller with Arria 10 EMIF Interfaces
  • Changed name of Generated Files for Memory Controllers with Arria 10 EMIF IP section to Generated Files for Arria 10 External Memory Interface IP, and revised content.
  • Revised content of General Settings for Arria 10 EMIF IP section.
  • Added Parameterizing Arria 10 External Memory Interface IP section.
  • Revised content of Memory Topology for LPDDR2, DDR3 and DDR4 SDRAM for Arria 10 EMIF IP section.
  • Added Memory Parameters for QDR IV for Arria 10 EMIF IP section.
  • Revised Memory Parameters for RLDRAM 3 for Arria 10 EMIF IP section.
  • Added slew rate information for QDR II, QDR II+, and QDR II+ Xtreme to table in Slew Rates for Arria 10 EMIF IP section.
  • Revised ISI Parameters table in Intersymbol Interference Channel Signal Integrity for UniPHY IP section.
  • Revised description of fly-by topology for UDIMMs in Board Skews for UniPHY IP section.
  • Added MAX 10 to Simulation Options table in Diagnostics for UniPHY IP section.
  • Added note to descriptions of Minimum delay difference between CK and DQS and Maximum delay difference between CK and DQS in Board Skew Parameters for LPDDR2/DDR2/DDR3 SDRAM section.
  • Revised content of Parameter Descriptions table in Board and Package Skews for LPDDR2/DDR3/DDR4 SDRAM for Arria 10 EMIF IP.
  • Revised content of Parameter Descriptions table in Board and Package Skews for QDR II, QDR II+, and QDR II+ Xtreme for Arria 10 EMIF IP.
  • Revised content of Parameter Descriptions table in Board and Package Skews for RLDRAM II and RLDRAM 3 for Arria 10 EMIF IP.
  • Revised content of Controller Settings table in Controller Settings for Arria 10 EMIF IP.
  • Added Diagnostics for Arria 10 EMIF IP.
December 2013 2013.12.16
  • Removed references to ALTMEMPHY.
  • Removed references to HardCopy.
  • Removed references to Stratix II devices.
  • Removed references to SOPC Builder.
  • Added Arria 10 information to Qsys Interface, Generated Files, Parameter Settings, Board Settings, and Controller Settings sections.
  • Added descriptions of several registered DIMM parameters to Memory Parameters for LPDDR2, DDR2, and DDR3 SDRAM table.
  • Added steps for compiling example project.
  • Added clock information to Adding Pins and DQ Group Assignments.
  • Updated Intersymbol Interference for UniPHY IP to Intersymbol Interference Channel Signal Integrity for UniPHY IP.
  • Added Intersymbol Interference Channel Signal Integrity for Arria 10 EMIF IP.
November 2012 6.0
  • Added RLDRAM 3 information.
  • Added LPDDR2 information.
  • Changed chapter number from 8 to 9.
June 2012 5.0
  • Added number of sharing interfaces parameters to Clock Parameters table.

  • Added DQ/DQS Package Deskew and Address/Command Package Deskew descriptions to Board Skew Parameters table.

  • Added equations for multiple boards to several parameter descriptions in Board Skew Parameters table.

  • Added Feedback icon.
November 2011 4.0
  • Updated Installation and Licensing section.
  • Combined Qsys and SOPC Builder Interfaces sections.

  • Combined parameter settings for DDR, DDR2, DDR3 SDRAM, QDRII SRAM, and RLDRAM II for both ALTMEMPHY and UniPHY IP.

  • Added parameter usage details to Parameterizing Memory Controllers with UniPHY IP section.

  • Moved Functional Description section for DDR, DDR2, DDR3 SDRAM, QDRII SRAM, and RLDRAM II to volume 3 of the External Memory Interface Handbook.

June 2011 3.0
  • Removed references to High-Performance Controller.
  • Updated High-Performance Controller II information.

  • Removed HardCopy III, HardCopy IV E, HardCopy IV GX, Stratix III, and Stratix IV support.

  • Updated Generated Files lists.
  • Added Qsys and SOPC Builder Interfaces section.
December 2010 2.1

  • Updated Design Flows and Generated Files information.

  • Updated Parameterizing Memory Controllers with UniPHY IP chapter

July 2010 2.0

  • Added information for new GUI parameters: Controller latency, Enable reduced bank tracking for area optimization, and Number of banks to track.

  • Removed information about IP Advisor. This feature is removed from the DDR/DDR2 SDRAM IP support for version 10.0.

February 2010 1.3 Corrected typos.
February 2010 1.2
  • Full support for Stratix IV devices.
  • Added timing diagrams for initialization and calibration stages for HPC.
November 2009 1.1 Minor corrections.
November 2009 1.0 Initial release.
Level Two Title