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Ixiasoft
Visible to Intel only — GUID: hco1416490962387
Ixiasoft
2. DDR2, DDR3, and DDR4 SDRAM Board Design Guidelines
The following areas are discussed:
- comparison of various types of termination schemes, and their effects on the signal quality on the receiver
- proper drive strength setting on the FPGA to optimize the signal integrity at the receiver
- effects of different loading types, such as components versus DIMM configuration, on signal quality
It is important to understand the trade-offs between different types of termination schemes, the effects of output drive strengths, and different loading types, so that you can swiftly navigate through the multiple combinations and choose the best possible settings for your designs.
The following key factors affect signal quality at the receiver:
- Leveling and dynamic ODT
- Proper use of termination
- Layout guidelines
As memory interface performance increases, board designers must pay closer attention to the quality of the signal seen at the receiver because poorly transmitted signals can dramatically reduce the overall data-valid margin at the receiver. The following figure shows the differences between an ideal and real signal seen by the receiver.
- Leveling and Dynamic Termination
- DDR2 Terminations and Guidelines
- DDR3 Terminations in Arria V, Cyclone V, Stratix III, Stratix IV, and Stratix V
- DDR3 and DDR4 on Arria 10 and Stratix 10 Devices
- Layout Approach
- Channel Signal Integrity Measurement
- Design Layout Guidelines
- Package Deskew
- Document Revision History