Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide

Download PDF
ID 683293
Date 8/24/2021
Public
Document Table of Contents
Document Table of Contents x
1. Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide
1. Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide x
1.1. Overview 1.2. PDN Decoupling Methodology Review 1.3. PDN Tool Setup and Result Optimization 1.4. Device-Specific PDN Tool 2.0 Known Issues and Their Solutions 1.5. Document Revision History for the Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide
1.2. PDN Decoupling Methodology Review x
1.2.1. PDN Circuit Topology 1.2.2. Major Tabs of the PDN Tool 2.0 1.2.3. Design PCB Decoupling Using the PDN Tool 2.0 1.2.4. Troubleshooting ZEFF
1.2.1. PDN Circuit Topology x
1.2.1.1. ZTARGET 1.2.1.2. FEFFECTIVE
1.2.2. Major Tabs of the PDN Tool 2.0 x
1.2.2.1. System_Decap 1.2.2.2. Stackup 1.2.2.3. BGA_Via 1.2.2.4. Plane_Cap 1.2.2.5. Cap_Mount 1.2.2.6. X2Y_Mount 1.2.2.7. Library 1.2.2.8. Enlarged_Graph
1.2.2.1. System_Decap x
1.2.2.1.1. Device Selection Section 1.2.2.1.2. Power Rail Data and Configuration Section 1.2.2.1.3. Meeting Target Impedance when Entering 0 A into the PDN Tool 1.2.2.1.4. Dealing with Multiple Shared Power Supply Pin Types 1.2.2.1.5. VRM Data Section 1.2.2.1.6. Rail Group Summary Section 1.2.2.1.7. VRM Impedance Section 1.2.2.1.8. BGA Via Section 1.2.2.1.9. Plane Section 1.2.2.1.10. Spreading Section 1.2.2.1.11. Implementing Split Planes 1.2.2.1.12. FEFFECTIVE Section 1.2.2.1.13. Decoupling Section 1.2.2.1.14. Results Summary Section 1.2.2.1.15. Recommended Flow for Deriving Decoupling for an FPGA System using the System_Decap Tab
1.2.2.2. Stackup x
1.2.2.2.1. Stackup Data 1.2.2.2.2. Full Stackup
1.2.2.7. Library x
1.2.2.7.1. Two-Terminal Decoupling Capacitors 1.2.2.7.2. Bulk Capacitors 1.2.2.7.3. X2Y Decoupling Capacitors 1.2.2.7.4. BGA Via and Plane Capacitance 1.2.2.7.5. VRM Library 1.2.2.7.6. Spreading R and L Parasitics 1.2.2.7.7. Dielectric Material Library 1.2.2.7.8. User Set FEFFECTIVE
1.2.3. Design PCB Decoupling Using the PDN Tool 2.0 x
1.2.3.1. Pre-Layout Instructions 1.2.3.2. Deriving Decoupling in a Single-Rail Scenario 1.2.3.3. Deriving Decoupling in the Power-Sharing Scenarios
1.2.4. Troubleshooting ZEFF x
1.2.4.1. Strategies for Correcting a High ZEFF
1.3. PDN Tool Setup and Result Optimization x
1.3.1. Setting Up a PCB Stackup 1.3.2. Setting up a Power Group 1.3.3. Optimizing in Pre-Layout 1.3.4. Further Optimizing for Better Accuracy 1.3.5. Correlation
1.3.1. Setting Up a PCB Stackup x
1.3.1.1. Selecting Your Device 1.3.1.2. Inputting Stackup Data
1.3.1.2. Inputting Stackup Data x
1.3.1.2.1. Using a Custom Dielectric Material
1.3.2. Setting up a Power Group x
1.3.2.1. Selecting the Rails 1.3.2.2. Rail Group Summary 1.3.2.3. VRM Impedance 1.3.2.4. BGA Via 1.3.2.5. Calculating Plane 1.3.2.6. Plane Spreading Parasitics 1.3.2.7. FEFFECTIVE and Decoupling Result Summary
1.3.3. Optimizing in Pre-Layout x
1.3.3.1. Checking the Capacitor Model 1.3.3.2. Optimizing the Decap Count
1. Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide

1.2.1.1. ZTARGET

The change of dynamic component of PDN current gives rise to voltage fluctuation within the PDN, which may lead to logic and timing issues. You can reduce excessive voltage fluctuation by reducing PDN impedance. One design guideline is target impedance, ZTARGET. In the frequency domain, voltage fluctuation across a circuit at a frequency is proportional to the current flow through the circuit, and the impedance of the circuit at the frequency according to Ohm’s law. ZTARGET is defined using the maximum allowable noise tolerance and dynamic current change, and is calculated as follows.

Figure 2. ZTARGET Equation

For example, the dynamic current of a 1.8 V power rail is 2 A. The worst case dynamic current change is 50% of the dynamic current. The noise tolerance of the power rail is 5% of the nominal voltage. The desired PDN target impedance for decoupling design is calculated as follows:

Figure 3. ZTARGET Example Equation

To accurately calculate the ZTARGET for any power rail, you must know the following information:

  • The maximum dynamic current change requirements for the FPGA that is powered by the power rail under consideration. You can obtain this information from respective device datasheet. You can calculate the maximum dynamic current change of a device using the maximum dynamic current and the dynamic current change percentage.
    Note: The dynamic current is intended to parameterize the high-frequency current draws required to provide the energy for CMOS transistors changing state. In the case of the core rail, the transients are generated by switching inside the FPGA core. Thus, a design which involves extensive logical switching generates higher % transients (dynamic current change) than a more static design. The dynamic current change magnitude can be higher if the dynamic current is higher. For information about default settings of the dynamic current change percentage for major FPGA rails, refer to the table in the Introduction tab of the PDN tool 2.0.
    Note: You can obtain accurate estimations on the maximum dynamic current for Intel® FPGA devices using the Early Power Estimator (EPE) tool or the Intel® Quartus® Prime software power Analyzer tools. When using the data from the EPE, be sure to use only the dynamic power for each section for the PDN calculation.
  • The maximum allowable noise tolerance on the power rail is given as a percentage of the supply voltage.

Device switching activity leads to transient noise (high frequency spikes) seen on the power supply rails. This noise can cause functionality issues if they are too high. The noise must be damped within a range defined as a percentage of power supply voltage. The recommended values for the maximum allowable noise tolerance are listed in the respective device datasheet and in the Introduction tab of the PDN tool 2.0. Different rails have different specifications because of their sensitivity to the transient voltage noise as well as how much current is used by the power rail.

Refer to the Introduction tab of the PDN tool 2.0 for more information about ZTARGET.

Table 2.  Settings for the Intel® Stratix® 10 Device Power RailsThis information is from the PDN tool 2.0 for a Intel® Stratix® 10 device.
Rail Name Default Voltage (V) Noise Tolerance (%) Dynamic Current Change (%) Description
VCC 0.8 - 0.94 1 5 30 - 50 Core (30% for high dynamic current; 50% for low dynamic current)
VCCERAM 0.9 5 50 Programmable Power Tech Aux
VCCR_GXB 1.03/1.12 1 3 30 L-Tile and H-Tile Transceiver RX Analog
VCCT_GXB 1.03/1.12 1 2 60 L-Tile and H-Tile Transceiver TX Analog
VCCRT_GXE 0.9 2 30 E-Tile Transceiver RX Analog
VCCRT_GXP 0.9 2 30 P-Tile Transceiver TX Analog
VCCPT 1.8 5 50 Programmable Power Tech
VCCA_PLL 1.8 5 10 PLL Analog
VCCH_GXB 1.8 3 15 L-Tile and H-Tile Transceiver I/O Buffer Block
VCCH_GXE 1.1 2 30 E-Tile Transceiver I/O Buffer Block
VCCH_GXP 1.8 2 30 P-Tile Transceiver I/O Buffer Block
VCCIO 1.2/1.25/1.35/1.5/1.8 5 100 I/O Banks
VCCP 0.8 - 0.94 1 5 33 Periphery Power Supply
VCCIO_UIB 1.2 2 100/71 2 Host Memory Buffer I/O Universal Interface Bus
VCCBAT 1.2/1.5/1.8 5 100 Battery Back-up Power Supply
Related Information
1 For more information about power rail functions, refer to the Pin Connection Guidelines for the selected device family.
2

If each VCCIO_UIB (BL or TL) is individually designed, use 100% of the total dynamic current.

If both VCCIO_UIBs (BL and TL) are combined:
  • If both HBM operations are coherent, use 100% of the total dynamic current.
  • If both HBM operations are non-coherent, use 71% of the total dynamic current.

The FEFFECTIVE for VCCIO_UIB at package level is 2 MHz to meet target impedance.

Level Two Title