Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide

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ID 683293
Date 8/24/2021
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Document Table of Contents
Document Table of Contents x
1. Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide
1. Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide x
1.1. Overview 1.2. PDN Decoupling Methodology Review 1.3. PDN Tool Setup and Result Optimization 1.4. Device-Specific PDN Tool 2.0 Known Issues and Their Solutions 1.5. Document Revision History for the Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide
1.2. PDN Decoupling Methodology Review x
1.2.1. PDN Circuit Topology 1.2.2. Major Tabs of the PDN Tool 2.0 1.2.3. Design PCB Decoupling Using the PDN Tool 2.0 1.2.4. Troubleshooting ZEFF
1.2.1. PDN Circuit Topology x
1.2.1.1. ZTARGET 1.2.1.2. FEFFECTIVE
1.2.2. Major Tabs of the PDN Tool 2.0 x
1.2.2.1. System_Decap 1.2.2.2. Stackup 1.2.2.3. BGA_Via 1.2.2.4. Plane_Cap 1.2.2.5. Cap_Mount 1.2.2.6. X2Y_Mount 1.2.2.7. Library 1.2.2.8. Enlarged_Graph
1.2.2.1. System_Decap x
1.2.2.1.1. Device Selection Section 1.2.2.1.2. Power Rail Data and Configuration Section 1.2.2.1.3. Meeting Target Impedance when Entering 0 A into the PDN Tool 1.2.2.1.4. Dealing with Multiple Shared Power Supply Pin Types 1.2.2.1.5. VRM Data Section 1.2.2.1.6. Rail Group Summary Section 1.2.2.1.7. VRM Impedance Section 1.2.2.1.8. BGA Via Section 1.2.2.1.9. Plane Section 1.2.2.1.10. Spreading Section 1.2.2.1.11. Implementing Split Planes 1.2.2.1.12. FEFFECTIVE Section 1.2.2.1.13. Decoupling Section 1.2.2.1.14. Results Summary Section 1.2.2.1.15. Recommended Flow for Deriving Decoupling for an FPGA System using the System_Decap Tab
1.2.2.2. Stackup x
1.2.2.2.1. Stackup Data 1.2.2.2.2. Full Stackup
1.2.2.7. Library x
1.2.2.7.1. Two-Terminal Decoupling Capacitors 1.2.2.7.2. Bulk Capacitors 1.2.2.7.3. X2Y Decoupling Capacitors 1.2.2.7.4. BGA Via and Plane Capacitance 1.2.2.7.5. VRM Library 1.2.2.7.6. Spreading R and L Parasitics 1.2.2.7.7. Dielectric Material Library 1.2.2.7.8. User Set FEFFECTIVE
1.2.3. Design PCB Decoupling Using the PDN Tool 2.0 x
1.2.3.1. Pre-Layout Instructions 1.2.3.2. Deriving Decoupling in a Single-Rail Scenario 1.2.3.3. Deriving Decoupling in the Power-Sharing Scenarios
1.2.4. Troubleshooting ZEFF x
1.2.4.1. Strategies for Correcting a High ZEFF
1.3. PDN Tool Setup and Result Optimization x
1.3.1. Setting Up a PCB Stackup 1.3.2. Setting up a Power Group 1.3.3. Optimizing in Pre-Layout 1.3.4. Further Optimizing for Better Accuracy 1.3.5. Correlation
1.3.1. Setting Up a PCB Stackup x
1.3.1.1. Selecting Your Device 1.3.1.2. Inputting Stackup Data
1.3.1.2. Inputting Stackup Data x
1.3.1.2.1. Using a Custom Dielectric Material
1.3.2. Setting up a Power Group x
1.3.2.1. Selecting the Rails 1.3.2.2. Rail Group Summary 1.3.2.3. VRM Impedance 1.3.2.4. BGA Via 1.3.2.5. Calculating Plane 1.3.2.6. Plane Spreading Parasitics 1.3.2.7. FEFFECTIVE and Decoupling Result Summary
1.3.3. Optimizing in Pre-Layout x
1.3.3.1. Checking the Capacitor Model 1.3.3.2. Optimizing the Decap Count
1. Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide

1.2.3.2. Deriving Decoupling in a Single-Rail Scenario

A power supply connects to only one power rail on the FPGA device in a single-rail scenario. The PDN noise is created by the dynamic current change of the single rail. You determine ZTARGET and FEFFECTIVE based on the parameters related to the selected rail only.

The PDN tool 2.0 provides two ways to derive a decoupling network. You can set up the tool with the information needed and let the tool derive the PDN decoupling for your system. You can also manually enter the information and derive decoupling. To derive the desired capacitor combination:

  1. Select the device/power rail to work with.
  2. Select the parameter settings for the PDN components.
  3. Enter the electric parameters to set ZTARGET and FEFFECTIVE.
    You need to have a good estimate of the parameters entered to derive the proper decoupling guidelines (ZTARGET and FEFFECTIVE). Although you need to determine those guidelines based on the worst-case scenario, pessimistic settings result in hard-to-achieve guidelines and over design of your PCB decoupling.
  4. Derive the PCB decoupling scheme.

    You must adjust the number and value of the PCB capacitors in the Decoupling Capacitor (Mid/High Frequency) and Decoupling Capacitor (Bulk) fields to keep the plotted ZEFF below ZTARGET until FEFFECTIVE. You can derive the decoupling for the selected power rail manually. You can also select the Auto Decouple button and let the PDN tool 2.0 automatically determine a decoupling solution. If you are not able to find a capacitor combination that meets your design goal, you can try to change the parameters at 2. For example, you can reduce the BGA via inductance used in the Calculate option by reducing the BGA via length in the BGA_VIA tab and using the low option for plane spreading. These changes reduce parasitic inductance and make it easier to achieve your decoupling goal. To achieve the low spreading setting, you must place the mid to high frequency PCB capacitors close to the FPGA device. You also must minimize the dielectric thickness between the power and ground plane. Refer to Troubleshooting ZEFF if the ZEFF is too high or the number of capacitors for decoupling becomes too high.

If you are not able to meet the ZTARGET requirement with the changes above, the PDN in your design may have reached its physical limitation under the electrical parameters you entered for ZTARGET and FEFFECTIVE. You should re-examine these parameters to check if they are overly pessimistic.

Figure 22. Enlarged Plot of ZEFF This sample impedance plot is for a 1SG280LU_F50 VCC power rail. Assume that the minimum voltage supply is 0.8 V, Idynamic is 50 A, dynamic current change is 30% of Idynamic, and the maximum allowable die noise tolerance is 5% of supply voltage. The VCC rail has 169 power BGA vias. The length of BGA via is assumed to be 20 mil.

The PDN tool 2.0 calculated that ZTARGET is 0.0027 Ω and FEFFECTIVE is 13.58 MHz. The figure above shows one of the capacitor combinations that you can select to meet the design goal. As shown in the plot, ZEFF remains under ZTARGET up to FEFFECTIVE. There are many combinations, but the ideal solution is to minimize the quantity and the type of capacitors needed to achieve a flat impedance profile below the ZTARGET.

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