Visible to Intel only — GUID: fel1595521918363
Ixiasoft
1.2.2.1.1. Device Selection Section
1.2.2.1.2. Power Rail Data and Configuration Section
1.2.2.1.3. Meeting Target Impedance when Entering 0 A into the PDN Tool
1.2.2.1.4. Dealing with Multiple Shared Power Supply Pin Types
1.2.2.1.5. VRM Data Section
1.2.2.1.6. Rail Group Summary Section
1.2.2.1.7. VRM Impedance Section
1.2.2.1.8. BGA Via Section
1.2.2.1.9. Plane Section
1.2.2.1.10. Spreading Section
1.2.2.1.11. Implementing Split Planes
1.2.2.1.12. FEFFECTIVE Section
1.2.2.1.13. Decoupling Section
1.2.2.1.14. Results Summary Section
1.2.2.1.15. Recommended Flow for Deriving Decoupling for an FPGA System using the System_Decap Tab
Visible to Intel only — GUID: fel1595521918363
Ixiasoft
1.4. Device-Specific PDN Tool 2.0 Known Issues and Their Solutions
Known Issue | Solution |
---|---|
Why does the PDN tool suggest 0 bulk decoupling capacitors with low-current power supply rails? | Low-Current Power Supply Rail Knowledge Base Article |
Should I enter Imax or IDynamic currents into the PDN tool? | Decoupling Current Knowledge Base Article |
Why can I not meet the target impedance when entering 0 mA into the PDN tool? | Impedance with 0 mA Knowledge Base Article |
Can I sum currents from multiple shared power supply pin types and enter them into a single supply pin type using the PDN tool? | Summing Power Supply Pin Types Knowledge Base Article |
Can I connect multiple power or GND pins to their planes through a single via with Intel® devices? | Using a Single Via Knowledge Base Article |
Why might the PDN tool's Auto Decoupling mode result in a ZEFF that is too high? | Auto Decoupling Mode Knowledge Base Article |
How do I use the PDN tool to optimize my PDN design? | AN 750: Using the PDN Tool to Optimize Your Power Delivery Network Design |