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1.2.2.1.1. Device Selection Section
1.2.2.1.2. Power Rail Data and Configuration Section
1.2.2.1.3. Meeting Target Impedance when Entering 0 A into the PDN Tool
1.2.2.1.4. Dealing with Multiple Shared Power Supply Pin Types
1.2.2.1.5. VRM Data Section
1.2.2.1.6. Rail Group Summary Section
1.2.2.1.7. VRM Impedance Section
1.2.2.1.8. BGA Via Section
1.2.2.1.9. Plane Section
1.2.2.1.10. Spreading Section
1.2.2.1.11. Implementing Split Planes
1.2.2.1.12. FEFFECTIVE Section
1.2.2.1.13. Decoupling Section
1.2.2.1.14. Results Summary Section
1.2.2.1.15. Recommended Flow for Deriving Decoupling for an FPGA System using the System_Decap Tab
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1.3.5. Correlation
The following results show the correlation between the PDN tool and the post-layout system PDN impedance profile (lower right figure) for one of Intel's development kit boards. In the post-layout analysis, the simple VRM model from the PDN tool was used. Since the PDN tool is already considering PKG and die parasitics, both results are well correlated.
Note: The PDN tool does not display the on-die capacitance in the result graph. Die capacitance is utilized for determining FEFFECTIVE.
Figure 42. PDN Tool