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Ixiasoft
1.2.2.1.1. Device Selection Section
1.2.2.1.2. Power Rail Data and Configuration Section
1.2.2.1.3. Meeting Target Impedance when Entering 0 A into the PDN Tool
1.2.2.1.4. Dealing with Multiple Shared Power Supply Pin Types
1.2.2.1.5. VRM Data Section
1.2.2.1.6. Rail Group Summary Section
1.2.2.1.7. VRM Impedance Section
1.2.2.1.8. BGA Via Section
1.2.2.1.9. Plane Section
1.2.2.1.10. Spreading Section
1.2.2.1.11. Implementing Split Planes
1.2.2.1.12. FEFFECTIVE Section
1.2.2.1.13. Decoupling Section
1.2.2.1.14. Results Summary Section
1.2.2.1.15. Recommended Flow for Deriving Decoupling for an FPGA System using the System_Decap Tab
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Ixiasoft
1.2.2.2.2. Full Stackup
This section lists the complete stackup of your board. You can modify content in the section to better match your board design. The last column in the section is the PWR plane types. In a single rail analysis case, assign the layer where the power rail is located as target, and the ground layer that the power rail refers to as reference.
Button Label | Description |
---|---|
Construct Stackup | Populates the Full Stackup section to the number of layers defined in the Stackup Data section. |
Import Geometries | Updates geometry parameters in the BGA_Via, Plane_Cap, Cap_Mount, and X2Y_Mount tabs using your input from the Stackup Data section. The tool also checks that the PWR Planes column in the Full Stackup section has only one target layer, and provides a warning for this error. |
Proceed to System Decap | Opens the System_Decap tab. |