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1.2.2.1.1. Device Selection Section
1.2.2.1.2. Power Rail Data and Configuration Section
1.2.2.1.3. Meeting Target Impedance when Entering 0 A into the PDN Tool
1.2.2.1.4. Dealing with Multiple Shared Power Supply Pin Types
1.2.2.1.5. VRM Data Section
1.2.2.1.6. Rail Group Summary Section
1.2.2.1.7. VRM Impedance Section
1.2.2.1.8. BGA Via Section
1.2.2.1.9. Plane Section
1.2.2.1.10. Spreading Section
1.2.2.1.11. Implementing Split Planes
1.2.2.1.12. FEFFECTIVE Section
1.2.2.1.13. Decoupling Section
1.2.2.1.14. Results Summary Section
1.2.2.1.15. Recommended Flow for Deriving Decoupling for an FPGA System using the System_Decap Tab
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1.3.3.2. Optimizing the Decap Count
Since the tool is a code-based spreadsheet, it keeps adding up the number of decoupling capacitors until ZPDN satisfies ZTARGET up to FEFFECTIVE. The PDN tool has a 301ea maximum decap count.
- Change the Decoupling mode from Auto to Manual.
There can be a ±5% variation on ZEFF impedance when doing decoupling caps optimization. This impedance variation can relate to fabrication tolerance.
Figure 35. Manual Decoupling Results Summary - Pre-Optimization - Observing the impedance plot carefully, optimize the number of each capacitor.
Figure 36. Manual Decoupling Results Summary - Post-Optimization, Round 1After optimizing manually, 301ea decaps are dramatically reduced to 124ea while maintaining a similar ZPDN profile (the red curve) under the same ZTARGET.Figure 37. Manual Decoupling Results Summary - Post-Optimization Results, Round 1A small amount of violation at different frequencies can reduce the number of decaps. Before and after results are shown below.