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Ixiasoft
1.2.2.1.1. Device Selection Section
1.2.2.1.2. Power Rail Data and Configuration Section
1.2.2.1.3. Meeting Target Impedance when Entering 0 A into the PDN Tool
1.2.2.1.4. Dealing with Multiple Shared Power Supply Pin Types
1.2.2.1.5. VRM Data Section
1.2.2.1.6. Rail Group Summary Section
1.2.2.1.7. VRM Impedance Section
1.2.2.1.8. BGA Via Section
1.2.2.1.9. Plane Section
1.2.2.1.10. Spreading Section
1.2.2.1.11. Implementing Split Planes
1.2.2.1.12. FEFFECTIVE Section
1.2.2.1.13. Decoupling Section
1.2.2.1.14. Results Summary Section
1.2.2.1.15. Recommended Flow for Deriving Decoupling for an FPGA System using the System_Decap Tab
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Ixiasoft
1.2.2.7.1. Two-Terminal Decoupling Capacitors
The decoupling capacitors section contains the default ESR and ESL values for the various two-terminal capacitors in the following footprints:
- 0201
- 0402
- 0603
- 0805
- 1206
The decoupling capacitors section also provides the option for user-defined capacitors (such as User1 through User4). You can define the ESR and ESL parasitics for the various footprints and enter the corresponding capacitor value in the System_Decap tab. Choose the corresponding footprint when defining the capacitor values.