Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide

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ID 683293
Date 8/24/2021
Public
Document Table of Contents
Document Table of Contents x
1. Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide
1. Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide x
1.1. Overview 1.2. PDN Decoupling Methodology Review 1.3. PDN Tool Setup and Result Optimization 1.4. Device-Specific PDN Tool 2.0 Known Issues and Their Solutions 1.5. Document Revision History for the Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide
1.2. PDN Decoupling Methodology Review x
1.2.1. PDN Circuit Topology 1.2.2. Major Tabs of the PDN Tool 2.0 1.2.3. Design PCB Decoupling Using the PDN Tool 2.0 1.2.4. Troubleshooting ZEFF
1.2.1. PDN Circuit Topology x
1.2.1.1. ZTARGET 1.2.1.2. FEFFECTIVE
1.2.2. Major Tabs of the PDN Tool 2.0 x
1.2.2.1. System_Decap 1.2.2.2. Stackup 1.2.2.3. BGA_Via 1.2.2.4. Plane_Cap 1.2.2.5. Cap_Mount 1.2.2.6. X2Y_Mount 1.2.2.7. Library 1.2.2.8. Enlarged_Graph
1.2.2.1. System_Decap x
1.2.2.1.1. Device Selection Section 1.2.2.1.2. Power Rail Data and Configuration Section 1.2.2.1.3. Meeting Target Impedance when Entering 0 A into the PDN Tool 1.2.2.1.4. Dealing with Multiple Shared Power Supply Pin Types 1.2.2.1.5. VRM Data Section 1.2.2.1.6. Rail Group Summary Section 1.2.2.1.7. VRM Impedance Section 1.2.2.1.8. BGA Via Section 1.2.2.1.9. Plane Section 1.2.2.1.10. Spreading Section 1.2.2.1.11. Implementing Split Planes 1.2.2.1.12. FEFFECTIVE Section 1.2.2.1.13. Decoupling Section 1.2.2.1.14. Results Summary Section 1.2.2.1.15. Recommended Flow for Deriving Decoupling for an FPGA System using the System_Decap Tab
1.2.2.2. Stackup x
1.2.2.2.1. Stackup Data 1.2.2.2.2. Full Stackup
1.2.2.7. Library x
1.2.2.7.1. Two-Terminal Decoupling Capacitors 1.2.2.7.2. Bulk Capacitors 1.2.2.7.3. X2Y Decoupling Capacitors 1.2.2.7.4. BGA Via and Plane Capacitance 1.2.2.7.5. VRM Library 1.2.2.7.6. Spreading R and L Parasitics 1.2.2.7.7. Dielectric Material Library 1.2.2.7.8. User Set FEFFECTIVE
1.2.3. Design PCB Decoupling Using the PDN Tool 2.0 x
1.2.3.1. Pre-Layout Instructions 1.2.3.2. Deriving Decoupling in a Single-Rail Scenario 1.2.3.3. Deriving Decoupling in the Power-Sharing Scenarios
1.2.4. Troubleshooting ZEFF x
1.2.4.1. Strategies for Correcting a High ZEFF
1.3. PDN Tool Setup and Result Optimization x
1.3.1. Setting Up a PCB Stackup 1.3.2. Setting up a Power Group 1.3.3. Optimizing in Pre-Layout 1.3.4. Further Optimizing for Better Accuracy 1.3.5. Correlation
1.3.1. Setting Up a PCB Stackup x
1.3.1.1. Selecting Your Device 1.3.1.2. Inputting Stackup Data
1.3.1.2. Inputting Stackup Data x
1.3.1.2.1. Using a Custom Dielectric Material
1.3.2. Setting up a Power Group x
1.3.2.1. Selecting the Rails 1.3.2.2. Rail Group Summary 1.3.2.3. VRM Impedance 1.3.2.4. BGA Via 1.3.2.5. Calculating Plane 1.3.2.6. Plane Spreading Parasitics 1.3.2.7. FEFFECTIVE and Decoupling Result Summary
1.3.3. Optimizing in Pre-Layout x
1.3.3.1. Checking the Capacitor Model 1.3.3.2. Optimizing the Decap Count
1. Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide

1.2.4.1. Strategies for Correcting a High ZEFF

As well as decoupling manually, you can reduce the decoupling burden by accurately estimating your current requirements and making your PCB more efficient. You may be able to achieve reduced PCB current requirements in the following ways:

  • Estimating realistic current requirements in the Early Power Estimator (EPE).
  • Entering realistic toggle rate figures for the logic in the EPE. Unrealistically high toggle rates dramatically increases dynamic current requirements.
  • Entering realistic logic requirements in the EPE.
  • Entering realistic clock frequencies in the EPE.
  • Using the Intel® Quartus® Prime software power analyzer and .vcd simulation entry for accurate current requirement estimation.
  • Considering Root Sum Squared (RSS) averaging for shared power supply rails. Refer to the Introduction tab of the PDN tool for more information about this method.

You can make the PCB more efficient in the following ways:

  • Increasing inter-plane capacitance of your Power (PWR) and Ground (GND) plane pair by reducing their dielectric thickness.
  • Increasing inter-plane capacitance of your PWR and GND plane pair by increasing their surface area.
  • Reducing loop inductance from the PWR and GND plane pair to the FPGA. You can do this by moving them closer to the surface of the PCB where the FPGA is mounted.
  • Reducing loop inductance from the high frequency decoupling capacitors to the PWR and GND plane pair. You can do this by placing them on the surface of the PCB that is closest to the planes.
  • Using Via On Side (VOS) instead of Via On End (VOE) capacitor mounting topologies to help at high frequencies.
  • Using ultra-low Effective Series Inductance (ESL) mounting capacitors to help at high frequencies, for example, X2Y package style.
  • Using ultra-low Effective Series Resistance (ESR) bulk capacitors to help at low frequencies.
  • Considering larger vias with less ESL.

Realistic tool entry can make decoupling easier to achieve. The following factors affect the calculation of ZTARGET:

  • An increase in dynamic current reduces ZTARGET and makes decoupling difficult to achieve. See the guidelines above.
  • Enter realistic noise or ripple figures into the PDN tool. Use the noise figure listed in the device and rail specific table in the Introduction tab of the PDN Tool. Unrealistic ripple requirements reduce ZTARGET and make decoupling difficult.
  • Enter realistic transient % figures into the PDN tool. Use the transient % figure listed in the device and rail specific table in the Introduction tab of the PDN Tool. Unrealistic transient % requirements reduce ZTARGET and make decoupling difficult.

The PDN Tool 2.0 includes the following new pessimism removal features to make decoupling the large core current manageable:

  • Core clock frequency
  • Current ramp up period
Note: These features are available only for the core rail.
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