Visible to Intel only — GUID: joc1409511035724
Ixiasoft
1.2.2.1.1. Device Selection Section
1.2.2.1.2. Power Rail Data and Configuration Section
1.2.2.1.3. Meeting Target Impedance when Entering 0 A into the PDN Tool
1.2.2.1.4. Dealing with Multiple Shared Power Supply Pin Types
1.2.2.1.5. VRM Data Section
1.2.2.1.6. Rail Group Summary Section
1.2.2.1.7. VRM Impedance Section
1.2.2.1.8. BGA Via Section
1.2.2.1.9. Plane Section
1.2.2.1.10. Spreading Section
1.2.2.1.11. Implementing Split Planes
1.2.2.1.12. FEFFECTIVE Section
1.2.2.1.13. Decoupling Section
1.2.2.1.14. Results Summary Section
1.2.2.1.15. Recommended Flow for Deriving Decoupling for an FPGA System using the System_Decap Tab
Visible to Intel only — GUID: joc1409511035724
Ixiasoft
1.2.2.1. System_Decap
You can determine the decoupling of selected FPGA devices based on the power sharing scheme entered in the System_Decap tab.
The System_Decap tab is divided into the following sections:
- Device selection
- Power rail data and configuration
- VRM Data
- Rail group summary
- VRM impedance
- BGA Via
- Plane
- Spreading
- FEFFECTIVE
- Decoupling selection
- Result summary
- Device Selection Section
- Power Rail Data and Configuration Section
- Meeting Target Impedance when Entering 0 A into the PDN Tool
- Dealing with Multiple Shared Power Supply Pin Types
- VRM Data Section
- Rail Group Summary Section
- VRM Impedance Section
- BGA Via Section
- Plane Section
- Spreading Section
- Implementing Split Planes
- FEFFECTIVE Section
- Decoupling Section
- Results Summary Section
- Recommended Flow for Deriving Decoupling for an FPGA System using the System_Decap Tab