Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide

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ID 683293
Date 8/24/2021
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Document Table of Contents
Document Table of Contents x
1. Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide
1. Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide x
1.1. Overview 1.2. PDN Decoupling Methodology Review 1.3. PDN Tool Setup and Result Optimization 1.4. Device-Specific PDN Tool 2.0 Known Issues and Their Solutions 1.5. Document Revision History for the Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide
1.2. PDN Decoupling Methodology Review x
1.2.1. PDN Circuit Topology 1.2.2. Major Tabs of the PDN Tool 2.0 1.2.3. Design PCB Decoupling Using the PDN Tool 2.0 1.2.4. Troubleshooting ZEFF
1.2.1. PDN Circuit Topology x
1.2.1.1. ZTARGET 1.2.1.2. FEFFECTIVE
1.2.2. Major Tabs of the PDN Tool 2.0 x
1.2.2.1. System_Decap 1.2.2.2. Stackup 1.2.2.3. BGA_Via 1.2.2.4. Plane_Cap 1.2.2.5. Cap_Mount 1.2.2.6. X2Y_Mount 1.2.2.7. Library 1.2.2.8. Enlarged_Graph
1.2.2.1. System_Decap x
1.2.2.1.1. Device Selection Section 1.2.2.1.2. Power Rail Data and Configuration Section 1.2.2.1.3. Meeting Target Impedance when Entering 0 A into the PDN Tool 1.2.2.1.4. Dealing with Multiple Shared Power Supply Pin Types 1.2.2.1.5. VRM Data Section 1.2.2.1.6. Rail Group Summary Section 1.2.2.1.7. VRM Impedance Section 1.2.2.1.8. BGA Via Section 1.2.2.1.9. Plane Section 1.2.2.1.10. Spreading Section 1.2.2.1.11. Implementing Split Planes 1.2.2.1.12. FEFFECTIVE Section 1.2.2.1.13. Decoupling Section 1.2.2.1.14. Results Summary Section 1.2.2.1.15. Recommended Flow for Deriving Decoupling for an FPGA System using the System_Decap Tab
1.2.2.2. Stackup x
1.2.2.2.1. Stackup Data 1.2.2.2.2. Full Stackup
1.2.2.7. Library x
1.2.2.7.1. Two-Terminal Decoupling Capacitors 1.2.2.7.2. Bulk Capacitors 1.2.2.7.3. X2Y Decoupling Capacitors 1.2.2.7.4. BGA Via and Plane Capacitance 1.2.2.7.5. VRM Library 1.2.2.7.6. Spreading R and L Parasitics 1.2.2.7.7. Dielectric Material Library 1.2.2.7.8. User Set FEFFECTIVE
1.2.3. Design PCB Decoupling Using the PDN Tool 2.0 x
1.2.3.1. Pre-Layout Instructions 1.2.3.2. Deriving Decoupling in a Single-Rail Scenario 1.2.3.3. Deriving Decoupling in the Power-Sharing Scenarios
1.2.4. Troubleshooting ZEFF x
1.2.4.1. Strategies for Correcting a High ZEFF
1.3. PDN Tool Setup and Result Optimization x
1.3.1. Setting Up a PCB Stackup 1.3.2. Setting up a Power Group 1.3.3. Optimizing in Pre-Layout 1.3.4. Further Optimizing for Better Accuracy 1.3.5. Correlation
1.3.1. Setting Up a PCB Stackup x
1.3.1.1. Selecting Your Device 1.3.1.2. Inputting Stackup Data
1.3.1.2. Inputting Stackup Data x
1.3.1.2.1. Using a Custom Dielectric Material
1.3.2. Setting up a Power Group x
1.3.2.1. Selecting the Rails 1.3.2.2. Rail Group Summary 1.3.2.3. VRM Impedance 1.3.2.4. BGA Via 1.3.2.5. Calculating Plane 1.3.2.6. Plane Spreading Parasitics 1.3.2.7. FEFFECTIVE and Decoupling Result Summary
1.3.3. Optimizing in Pre-Layout x
1.3.3.1. Checking the Capacitor Model 1.3.3.2. Optimizing the Decap Count
1. Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide

1.3.4. Further Optimizing for Better Accuracy

While the two methods described in Optimizing in Pre-Layout are mainly used in the pre-layout stage for a rough estimation of the decoupling solution, the method described here shows how to get a more accurate and optimized estimation.
While Checking the Capacitor Model updates the decoupling capacitor library with the actual models used and Optimizing the Decap Count controls the number of decaps in manual mode, this method shows how to exclude Spreading R and L from the estimation process. As shown in the figure below, there is no mechanical restriction in populating decaps on the other side of the FPGA and red boxes indicate 70ea of 0402in decaps which can be directly placed; the majority of the total 124ea decaps can be populated right under BGAs. Thus, the spreading option might be negligible in this case.
Figure 38. Populating Decaps on the Other Side of the FPGA
  1. Change Feffective option from Calculate to Override.
  2. Check whether or not the number remains the same.
  3. If the number changes, write the recommended FEFFECTIVE, 10.18 MHz in the example below, into the white blank.
    Figure 39. FEFFECTIVE Override
  4. Change the Spreading option from Low to Ignore.
    Once the spreading option is ignored, the entire ZPDN is lowered a little, which means more margin.
    Figure 40. Ignoring Spreading
  5. Repeat the manual optimization for each cap as shown in Optimizing the Decap Count.
    After the optimization process, only 48ea of 0402in capacitors (circled with a red box below) are estimated while the total allowable number of 0402in capacitors is 70ea. Also, the rest of the larger capacitors (circled with a blue box below) in this example can be populated in the BGA area. Final results are shown below. The total number of capacitors was decreased down to 77ea from the max limit of 301ea, including bulk capacitors, through round 1 and 2 of the optimization process.
    Note: The PDN tool result already includes the bulk capacitor solution for VRM. However, Intel recommends checking with the VRM vendor about the required output capacitance to check if the PDN tool estimation can cover the requirement. Intel® Enpirion® models in the VRM library already include the required output capacitance. For the required capacitor combination, please refer to the datasheet of each VRM model.
    Figure 41. Manual Decoupling Results Summary - Post-Optimization, Round 2
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