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1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. HDMI 2.0 Design Example (Support FRL = 0)
4. HDCP Over HDMI 2.0/2.1 Design Example
5. HDMI Intel® Arria® 10 FPGA IP Design Example User Guide Archives
6. Revision History for HDMI Intel® Arria® 10 FPGA IP Design Example User Guide
2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram
2.2. Creating RX-Only or TX-Only Designs
2.3. Hardware and Software Requirements
2.4. Directory Structure
2.5. Design Components
2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
2.7. Design Software Flow
2.8. Running the Design in Different FRL Rates
2.9. Clocking Scheme
2.10. Interface Signals
2.11. Design RTL Parameters
2.12. Hardware Setup
2.13. Simulation Testbench
2.14. Design Limitations
2.15. Debugging Features
2.16. Upgrading Your Design
3.1. HDMI 2.0 RX-TX Retransmit Design Block Diagram
3.2. Hardware and Software Requirements
3.3. Directory Structure
3.4. Design Components
3.5. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
3.6. Clocking Scheme
3.7. Interface Signals
3.8. Design RTL Parameters
3.9. Hardware Setup
3.10. Simulation Testbench
3.11. Upgrading Your Design
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2.13. Simulation Testbench3.10. Simulation Testbench
The simulation testbench simulates the HDMI TX serial loopback to the RX core.
Note: This simulation testbench is not supported for designs with the Include I2C parameter enabled.
Figure 19. HDMI Intel® FPGA IP Simulation Testbench Block Diagram
Component | Description |
---|---|
Video TPG | The video test pattern generator (TPG) provides the video stimulus. |
Audio Sample Gen | The audio sample generator provides audio sample stimulus. The generator generates an incrementing test data pattern to be transmitted through the audio channel. |
Aux Sample Gen | The aux sample generator provides the auxiliary sample stimulus. The generator generates a fixed data to be transmitted from the transmitter. |
CRC Check | This checker verifies if the TX transceiver recovered clock frequency matches the desired data rate. |
Audio Data Check | The audio data check compares whether the incrementing test data pattern is received and decoded correctly. |
Aux Data Check | The aux data check compares whether the expected aux data is received and decoded correctly on the receiver side. |
The HDMI simulation testbench does the following verification tests:
HDMI Feature | Verification |
---|---|
Video data |
|
Auxiliary data |
|
Audio data |
|
A successful simulation ends with the following message:
# SYMBOLS_PER_CLOCK = 2
# VIC = 4
# FRL_RATE = 0
# BPP = 0
# AUDIO_FREQUENCY (kHz) = 48
# AUDIO_CHANNEL = 8
# Simulation pass
Simulator | Verilog HDL | VHDL |
---|---|---|
ModelSim* - Intel® FPGA Edition/ ModelSim* - Intel® FPGA Starter Edition | Yes | Yes |
VCS* / VCS* MX | Yes | Yes |
Riviera-PRO* | Yes | Yes |
Xcelium* Parallel | Yes | No |