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1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. HDMI 2.0 Design Example (Support FRL = 0)
4. HDCP Over HDMI 2.0/2.1 Design Example
5. HDMI Intel® Arria® 10 FPGA IP Design Example User Guide Archives
6. Revision History for HDMI Intel® Arria® 10 FPGA IP Design Example User Guide
2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram
2.2. Creating RX-Only or TX-Only Designs
2.3. Hardware and Software Requirements
2.4. Directory Structure
2.5. Design Components
2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
2.7. Design Software Flow
2.8. Running the Design in Different FRL Rates
2.9. Clocking Scheme
2.10. Interface Signals
2.11. Design RTL Parameters
2.12. Hardware Setup
2.13. Simulation Testbench
2.14. Design Limitations
2.15. Debugging Features
2.16. Upgrading Your Design
3.1. HDMI 2.0 RX-TX Retransmit Design Block Diagram
3.2. Hardware and Software Requirements
3.3. Directory Structure
3.4. Design Components
3.5. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
3.6. Clocking Scheme
3.7. Interface Signals
3.8. Design RTL Parameters
3.9. Hardware Setup
3.10. Simulation Testbench
3.11. Upgrading Your Design
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1.1. Generating the Design
Use the HDMI Intel® FPGA IP parameter editor in the Intel® Quartus® Prime software to generate the design examples.
Figure 2. Generating the Design Flow
- Create a project targeting Intel® Arria® 10 device family and select the desired device.
- In the IP Catalog, locate and double-click Interface Protocols > Audio & Video > HDMI Intel® FPGA IP . The New IP Variant or New IP Variation window appears.
- Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip or <your_ip>.qsys.
- Click OK. The parameter editor appears.
- On the IP tab, configure the desired parameters for both TX and RX.
- Turn on the Support FRL parameter to generate the HDMI 2.1 design example in FRL mode. Turn it off to generate the HDMI 2.0 design example without FRL.
- On the Design Example tab, select Arria 10 HDMI RX-TX Retransmit.
- Select Simulation to generate the testbench, and select Synthesis to generate the hardware design example.
You must select at least one of these options to generate the design example files. If you select both, the generation time is longer.
- For Generate File Format, select Verilog or VHDL.
- For Target Development Kit, select Intel® Arria® 10 GX FPGA Development Kit. If you select a development kit, then the target device (selected in step 4) changes to match the device on target board. For Intel® Arria® 10 GX FPGA Development Kit, the default device is 10AX115S2F4I1SG.
- Click Generate Example Design.