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1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. HDMI 2.0 Design Example (Support FRL = 0)
4. HDCP Over HDMI 2.0/2.1 Design Example
5. HDMI Intel® Arria® 10 FPGA IP Design Example User Guide Archives
6. Revision History for HDMI Intel® Arria® 10 FPGA IP Design Example User Guide
2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram
2.2. Creating RX-Only or TX-Only Designs
2.3. Hardware and Software Requirements
2.4. Directory Structure
2.5. Design Components
2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
2.7. Design Software Flow
2.8. Running the Design in Different FRL Rates
2.9. Clocking Scheme
2.10. Interface Signals
2.11. Design RTL Parameters
2.12. Hardware Setup
2.13. Simulation Testbench
2.14. Design Limitations
2.15. Debugging Features
2.16. Upgrading Your Design
3.1. HDMI 2.0 RX-TX Retransmit Design Block Diagram
3.2. Hardware and Software Requirements
3.3. Directory Structure
3.4. Design Components
3.5. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
3.6. Clocking Scheme
3.7. Interface Signals
3.8. Design RTL Parameters
3.9. Hardware Setup
3.10. Simulation Testbench
3.11. Upgrading Your Design
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4.6.2. Modifying HDCP Software Parameters
To facilitate the HDCP debugging process, you can modify the parameters in hdcp.c. The table below summarizes the list of configurable parameters and their functions.
Parameter | Function |
SUPPORT_HDCP1X | Enable HDCP 1.4 on TX side |
SUPPORT_HDCP2X | Enable HDCP 2.3 on TX side |
DEBUG_MODE_HDCP | Enable debug messages for TX HDCP |
REPEATER_MODE | Enable repeater mode for HDCP design example |
To modify the parameters, change the values to the desired values in hdcp.c. Before starting the compilation, make the following change in the build_sw_hdcp.sh:
- Locate the following line and comment it out to prevent the modified software file being replaced by the original files from the Intel® Quartus® Prime Software installation path.
- Run “./build_sw_hdcp.sh” to compile the updated software.
- The generated .elf file can be included into the design through two methods:
- Run “nios2-download -g <elf file name>”. Reset the system after the downloading process is completed to ensure proper functionality.
- Run “quartus_cdb –-update_mif” to update the memory initialization files. Run assembler to generate new .sof file which includes the updated software.