3.7. Interface Signals
Signal | Direction | Width | Description |
---|---|---|---|
On-board Oscillator Signal | |||
clk_fpga_b3_p | Input |
1 | 100 MHz free running clock for core reference clock |
REFCLK_FMCB_P ( Intel® Quartus® Prime Pro Edition) | Input | 1 | 625 MHz free running clock for transceiver reference clock; this clock can be of any frequency |
User Push Buttons and LEDs | |||
user_pb | Input |
1 | Push button to control the HDMI Intel® FPGA IP design functionality |
cpu_resetn | Input |
1 | Global reset |
user_led_g | Output |
4 |
Green LED display Refer to Hardware Setup for more information about the LED functions. |
user_led_r | Output |
4 |
Red LED display Refer to Hardware Setup for more information about the LED functions. |
HDMI FMC Daughter Card Pins on FMC Port B | |||
fmcb_gbtclk_m2c_p_0 | Input |
1 |
HDMI RX TMDS clock |
fmcb_dp_m2c_p | Input |
3 | HDMI RX red, green, and blue data channels
|
fmcb_dp_c2m_p | Output |
4 | HDMI TX clock, red, green, and blue data channels
|
fmcb_la_rx_p_9 | Input |
1 | HDMI RX +5V power detect |
fmcb_la_rx_p_8 | Inout |
1 | HDMI RX hot plug detect |
fmcb_la_rx_n_8 | Inout |
1 | HDMI RX I2C SDA for DDC and SCDC |
fmcb_la_tx_p_10 | Input |
1 | HDMI RX I2C SCL for DDC and SCDC |
fmcb_la_tx_p_12 | Input |
1 | HDMI TX hot plug detect |
fmcb_la_tx_n_12 | Inout |
1 | HDMI I2C SDA for DDC and SCDC |
fmcb_la_rx_p_10 | Inout |
1 | HDMI I2C SCL for DDC and SCDC |
fmcb_la_tx_p_11 | Inout |
1 | HDMI I2C SDA for redriver control |
fmcb_la_rx_n_9 | Inout |
1 | HDMI I2C SCL for redriver control |
Signal | Direction | Width | Description |
---|---|---|---|
Clock and Reset Signals | |||
mgmt_clk | Input |
1 | System clock input (100 MHz) |
fr_clk ( Intel® Quartus® Prime Pro Edition) | Input | 1 | Free running clock (625 MHz) for primary transceiver reference clock. This clock is required for transceiver calibration during power-up state. This clock can be of any frequency. |
reset | Input |
1 | System reset input |
reset_xcvr_powerup ( Intel® Quartus® Prime Pro Edition) | Input | 1 | Transceiver reset input. This signal is asserted during the reference clocks switching process (from free running clock to TMDS clock) in power-up state. |
tmds_clk_in | Input |
1 | HDMI RX TMDS clock |
i2c_clk | Input |
1 | Clock input for DDC and SCDC interface |
vid_clk_out | Output |
1 | Video clock output |
ls_clk_out | Output |
1 | Link speed clock output |
sys_init | Output |
1 | System initialization to reset the system upon power-up |
RX Transceiver and IOPLL Signals | |||
rx_serial_data | Input |
3 | HDMI serial data to the RX Native PHY |
gxb_rx_ready | Output |
1 | Indicates RX Native PHY is ready |
gxb_rx_cal_busy_out | Output |
3 | RX Native PHY calibration busy to the transceiver arbiter |
gxb_rx_cal_busy_in | Input |
3 | Calibration busy signal from the transceiver arbiter to the RX Native PHY |
iopll_locked | Output |
1 | Indicate IOPLL is locked |
gxb_reconfig_write | Input |
3 | Transceiver reconfiguration Avalon-MM interface from the RX Native PHY to the transceiver arbiter |
gxb_reconfig_read | Input |
3 | |
gxb_reconfig_address | Input |
30 |
|
gxb_reconfig_writedata | Input |
96 | |
gxb_reconfig_readdata | Output |
96 | |
gxb_reconfig_waitrequest | Output |
3 | |
RX Reconfiguration Management | |||
rx_reconfig_en | Output |
1 | RX Reconfiguration enables signal |
measure | Output |
24 | HDMI RX TMDS clock frequency measurement (in 10 ms) |
measure_valid | Output |
1 | Indicates the measure signal is valid |
os | Output |
1 |
Oversampling factor:
|
reconfig_mgmt_write | Output |
1 | RX reconfiguration management Avalon memory-mapped interface to transceiver arbiter |
reconfig_mgmt_read | Output |
1 | |
reconfig_mgmt_address | Output |
12 |
|
reconfig_mgmt_writedata | Output |
32 | |
reconfig_mgmt_readdata | Input |
32 | |
reconfig_mgmt_waitrequest | Input |
1 | |
HDMI RX Core Signals | |||
TMDS_Bit_clock_Ratio | Output |
1 | SCDC register interfaces |
audio_de | Output |
1 | HDMI RX core audio interfaces Refer to the Sink Interfaces section in the HDMI Intel® FPGA IP User Guide for more information. |
audio_data | Output |
256 | |
audio_info_ai | Output |
48 | |
audio_N | Output |
20 | |
audio_CTS | Output |
20 | |
audio_metadata | Output |
165 | |
audio_format | Output |
5 | |
aux_pkt_data | Output |
72 | HDMI RX core auxiliary interfaces Refer to the Sink Interfaces section in the HDMI Intel® FPGA IP User Guide for more information. |
aux_pkt_addr | Output |
6 | |
aux_pkt_wr | Output |
1 | |
aux_data | Output |
72 | |
aux_sop | Output |
1 | |
aux_eop | Output |
1 | |
aux_valid | Output |
1 | |
aux_error | Output |
1 | |
gcp | Output |
6 | HDMI RX core sideband signals Refer to the Sink Interfaces section in the HDMI Intel® FPGA IP User Guide for more information. |
info_avi | Output |
112 | |
info_vsi | Output |
61 | |
colordepth_mgmt_sync | Output |
2 | |
vid_data | Output |
N*48 | HDMI RX core video ports
Note: N = symbols per clock
Refer to the Sink Interfaces section in the HDMI Intel® FPGA IP User Guide for more information. |
vid_vsync | Output |
N | |
vid_hsync | Output |
N | |
vid_de | Output |
N | |
mode | Output |
1 | HDMI RX core control and status ports
Note: N = symbols per clock
Refer to the Sink Interfaces section in the HDMI Intel® FPGA IP User Guide for more information. |
ctrl | Output |
N*6 | |
locked | Output |
3 | |
vid_lock | Output |
1 | |
in_5v_power | Input |
1 | HDMI RX 5V detect and hotplug detect Refer to the Sink Interfaces section in the HDMI Intel® FPGA IP User Guide for more information. |
hdmi_rx_hpd_n | Inout |
1 | |
I2C Signals | |||
hdmi_rx_i2c_sda | Inout |
1 | HDMI RX DDC and SCDC interface |
hdmi_rx_i2c_scl | Inout |
1 | |
RX EDID RAM Signals | |||
edid_ram_access | Input |
1 | HDMI RX EDID RAM access interface. Assert edid_ram_access when you want to write or read from the EDID RAM, else this signal should be kept low. |
edid_ram_address | Input |
8 | |
edid_ram_write | Input |
1 | |
edid_ram_read | Input |
1 | |
edid_ram_readdata | Output |
8 | |
edid_ram_writedata | Input |
8 | |
edid_ram_waitrequest | Output |
1 |
Signal | Direction | Width | Description |
---|---|---|---|
Clock and Reset Signals | |||
mgmt_clk | Input |
1 | System clock input (100 MHz) |
fr_clk ( Intel® Quartus® Prime Pro Edition) | Input | 1 | Free running clock (625 MHz) for primary transceiver reference clock. This clock is required for transceiver calibration during power-up state. This clock can be of any frequency. |
reset | Input |
1 | System reset input |
hdmi_clk_in | Input |
1 | Reference clock to TX IOPLL and TX PLL. The clock frequency is the same as the TMDS clock frequency. |
vid_clk_out | Output |
1 | Video clock output |
ls_clk_out | Output |
1 |
Link speed clock output |
sys_init | Output |
1 | System initialization to reset the system upon power-up |
reset_xcvr | Input |
1 | Reset to TX transceiver |
reset_pll | Input |
1 | Reset to IOPLL and TX PLL |
reset_pll_reconfig | Output |
1 | Reset to PLL reconfiguration |
TX Transceiver and IOPLL Signals | |||
tx_serial_data | Output |
4 | HDMI serial data from the TX Native PHY |
gxb_tx_ready | Output |
1 | Indicates TX Native PHY is ready |
gxb_tx_cal_busy_out | Output |
4 | TX Native PHY calibration busy signal to the transceiver arbiter |
gxb_tx_cal_busy_in | Input |
4 | Calibration busy signal from the transceiver arbiter to the TX Native PHY |
iopll_locked | Output |
1 | Indicate IOPLL is locked |
txpll_locked | Output |
1 | Indicate TX PLL is locked |
gxb_reconfig_write | Input |
4 | Transceiver reconfiguration Avalon memory-mapped interface from the TX Native PHY to the transceiver arbiter |
gxb_reconfig_read | Input |
4 | |
gxb_reconfig_address | Input |
40 |
|
gxb_reconfig_writedata | Input |
128 | |
gxb_reconfig_readdata | Output |
128 | |
gxb_reconfig_waitrequest | Output |
4 | |
TX IOPLL and TX PLL Reconfiguration Signals | |||
pll_reconfig_write/tx_pll_reconfig_write | Input |
1 | TX IOPLL/TX PLL reconfiguration Avalon memory-mapped interfaces |
pll_reconfig_read/tx_pll_reconfig_read | Input |
1 | |
pll_reconfig_address/tx_pll_reconfig_address | Input |
10 | |
pll_reconfig_writedata/tx_pll_reconfig_writedata | Input |
32 | |
pll_reconfig_readdata/tx_pll_reconfig_readdata | Output |
32 | |
pll_reconfig_waitrequest/tx_pll_reconfig_waitrequest | Output |
1 | |
os | Input |
2 |
Oversampling factor:
|
measure | Input |
24 | Indicates the TMDS clock frequency of the transmitting video resolution. |
HDMI TX Core Signals | |||
ctrl | Input |
6*N | HDMI TX core control interfaces
Note: N = Symbols per clock
Refer to the Source Interfaces section in the HDMI Intel® FPGA IP User Guide for more information. |
mode | Input |
1 | |
TMDS_Bit_clock_Ratio | Input |
1 | SCDC register interfaces Refer to the Source Interfaces section in the HDMI Intel® FPGA IP User Guide for more information. |
Scrambler_Enable | Input |
1 | |
audio_de | Input |
1 | HDMI TX core audio interfaces Refer to the Source Interfaces section in the HDMI Intel® FPGA IP User Guide for more information. |
audio_mute | Input | 1 | |
audio_data | Input |
256 | |
audio_info_ai | Input |
49 | |
audio_N | Input |
22 | |
audio_CTS | Input |
22 | |
audio_metadata | Input |
166 | |
audio_format | Input |
5 | |
i2c_master_write | Input |
1 | TX I2C master Avalon® memory-mapped interface to I2C master inside the TX core.
Note: These signals are available only when you turn on the Include I2C parameter.
|
i2c_master_read | Input |
1 | |
i2c_master_address | Input |
4 | |
i2c_master_writedata | Input |
32 | |
i2c_master_readdata | Output |
32 | |
aux_ready | Output |
1 | HDMI TX core auxiliary interfaces Refer to the Source Interfaces section in the HDMI Intel® FPGA IP User Guide for more information. |
aux_data | Input |
72 | |
aux_sop | Input |
1 | |
aux_eop | Input |
1 | |
aux_valid | Input |
1 | |
gcp | Input |
6 | HDMI TX core sideband signals Refer to the Source Interfaces section in the HDMI Intel® FPGA IP User Guide for more information. |
info_avi | Input |
113 | |
info_vsi | Input |
62 | |
vid_data | Input |
N*48 | HDMI TX core video ports
Note: N = symbols per clock
Refer to the Source Interfaces section in the HDMI Intel® FPGA IP User Guide for more information. |
vid_vsync | Input |
N | |
vid_hsync | Input |
N | |
vid_de | Input |
N | |
I2C and Hot Plug Detect Signals | |||
nios_tx_i2c_sda_in ( Intel® Quartus® Prime Pro Edition)
Note: When you turn on the Include I2C parameter, this signal is placed in the TX core and will not be visible at this level.
|
Output |
1 | I2C Master Avalon® memory-mapped interfaces |
nios_tx_i2c_scl_in ( Intel® Quartus® Prime Pro Edition)
Note: When you turn on the Include I2C parameter, this signal is placed in the TX core and will not be visible at this level.
|
Output |
1 | |
nios_tx_i2c_sda_oe ( Intel® Quartus® Prime Pro Edition)
Note: When you turn on the Include I2C parameter, this signal is placed in the TX core and will not be visible at this level.
|
Input |
1 | |
nios_tx_i2c_scl_oe ( Intel® Quartus® Prime Pro Edition)
Note: When you turn on the Include I2C parameter, this signal is placed in the TX core and will not be visible at this level.
|
Input |
1 | |
nios_ti_i2c_sda_in ( Intel® Quartus® Prime Pro Edition) | Output |
1 | |
nios_ti_i2c_scl_in ( Intel® Quartus® Prime Pro Edition) | Output |
1 | |
nios_ti_i2c_sda_oe ( Intel® Quartus® Prime Pro Edition) | Input |
1 | |
nios_ti_i2c_scl_oe ( Intel® Quartus® Prime Pro Edition) | Input | 1 | |
hdmi_tx_i2c_sda | Inout |
1 | HDMI TX DDC and SCDC interfaces |
hdmi_tx_i2c_scl | Inout |
1 | |
hdmi_ti_i2c_sda ( Intel® Quartus® Prime Pro Edition) | Inout | 1 | I2C interface for Bitec Daughter Card Revision 11 TI181 Control |
hdmi_tx_ti_i2c_sda ( Intel® Quartus® Prime Standard Edition) | Inout | 1 | |
hdmi_ti_i2c_scl ( Intel® Quartus® Prime Pro Edition) | Inout | 1 | |
hdmi_tx_ti_i2c_scl ( Intel® Quartus® Prime Standard Edition) | Inout | 1 | |
tx_i2c_avalon_waitrequest |
Output | 1 | Avalon memory-mapped interfaces of I2C master |
tx_i2c_avalon_address ( Intel® Quartus® Prime Standard Edition) |
Input | 3 | |
tx_i2c_avalon_writedata ( Intel® Quartus® Prime Standard Edition) | Input | 8 | |
tx_i2c_avalon_readdata ( Intel® Quartus® Prime Standard Edition) |
Output | 8 | |
tx_i2c_avalon_chipselect ( Intel® Quartus® Prime Standard Edition) |
Input | 1 | |
tx_i2c_avalon_write ( Intel® Quartus® Prime Standard Edition) |
Input | 1 | |
tx_i2c_irq ( Intel® Quartus® Prime Standard Edition) |
Output | 1 | |
tx_ti_i2c_avalon_waitrequest ( Intel® Quartus® Prime Standard Edition) |
Output | 1 | |
tx_ti_i2c_avalon_address ( Intel® Quartus® Prime Standard Edition) | Input | 3 | |
tx_ti_i2c_avalon_writedata ( Intel® Quartus® Prime Standard Edition) | Input | 8 | |
tx_ti_i2c_avalon_readdata ( Intel® Quartus® Prime Standard Edition) | Output | 8 | |
tx_ti_i2c_avalon_chipselect ( Intel® Quartus® Prime Standard Edition) | Input | 1 | |
tx_ti_i2c_avalon_write ( Intel® Quartus® Prime Standard Edition) | Input | 1 | |
tx_ti_i2c_irq ( Intel® Quartus® Prime Standard Edition) | Output | 1 | |
hdmi_tx_hpd_n | Input |
1 | HDMI TX hotplug detect interfaces |
tx_hpd_ack | Input |
1 | |
tx_hpd_req | Output |
1 |
Signal | Direction | Width | Description |
---|---|---|---|
clk | Input |
1 | Reconfiguration clock. This clock must share the same clock with the reconfiguration management blocks. |
reset | Input |
1 | Reset signal. This reset must share the same reset with the reconfiguration management blocks. |
rx_rcfg_en | Input |
1 | RX reconfiguration enable signal |
tx_rcfg_en | Input |
1 | TX reconfiguration enable signal |
rx_rcfg_ch | Input |
2 | Indicates which channel to be reconfigured on the RX core. This signal must always remain asserted. |
tx_rcfg_ch | Input |
2 | Indicates which channel to be reconfigured on the TX core. This signal must always remain asserted. |
rx_reconfig_mgmt_write | Input |
1 | Reconfiguration Avalon-MM interfaces from the RX reconfiguration management |
rx_reconfig_mgmt_read | Input |
1 | |
rx_reconfig_mgmt_address | Input |
10 |
|
rx_reconfig_mgmt_writedata | Input |
32 | |
rx_reconfig_mgmt_readdata | Output |
32 | |
rx_reconfig_mgmt_waitrequest | Output |
1 | |
tx_reconfig_mgmt_write | Input |
1 | Reconfiguration Avalon-MM interfaces from the TX reconfiguration management |
tx_reconfig_mgmt_read | Input |
1 | |
tx_reconfig_mgmt_address | Input |
10 |
|
tx_reconfig_mgmt_writedata | Input |
32 | |
tx_reconfig_mgmt_readdata | Output |
32 | |
tx_reconfig_mgmt_waitrequest | Output |
1 | |
reconfig_write | Output |
1 | Reconfiguration Avalon-MM interfaces to the transceiver |
reconfig_read | Output |
1 | |
reconfig_address | Output |
10 |
|
reconfig_writedata | Output |
32 | |
rx_reconfig_readdata | Input |
32 | |
rx_reconfig_waitrequest | Input |
1 | |
tx_reconfig_readdata | Input |
1 | |
tx_reconfig_waitrequest | Input |
1 | |
rx_cal_busy | Input |
1 | Calibration status signal from the RX transceiver |
tx_cal_busy | Input |
1 | Calibration status signal from the TX transceiver |
rx_reconfig_cal_busy | Output |
1 | Calibration status signal to the RX transceiver PHY reset control |
tx_reconfig_cal_busy | Output |
1 | Calibration status signal from the TX transceiver PHY reset control |
Signal | Direction | Width | Description |
---|---|---|---|
reset | Input |
1 | Reset to the video/audio/auxiliary/sidebands FIFO buffer. |
hdmi_tx_ls_clk | Input |
1 | HDMI TX link speed clock |
hdmi_rx_ls_clk | Input |
1 | HDMI RX link speed clock |
hdmi_tx_vid_clk | Input |
1 | HDMI TX video clock |
hdmi_rx_vid_clk | Input |
1 | HDMI RX video clock |
hdmi_rx_locked | Input |
3 | Indicates HDMI RX locked status |
hdmi_rx_de | Input |
N | HDMI RX video interfaces
Note: N = symbols per clock
|
hdmi_rx_hsync | Input |
N | |
hdmi_rx_vsync | Input |
N | |
hdmi_rx_data | Input |
N*48 | |
rx_audio_format | Input |
5 | HDMI RX audio interfaces |
rx_audio_metadata | Input |
165 | |
rx_audio_info_ai | Input |
48 | |
rx_audio_CTS | Input |
20 | |
rx_audio_N | Input |
20 | |
rx_audio_de | Input |
1 | |
rx_audio_data | Input |
256 | |
rx_gcp | Input |
6 | HDMI RX sideband interfaces |
rx_info_avi | Input |
112 | |
rx_info_vsi | Input |
61 | |
rx_aux_eop | Input |
1 | HDMI RX auxiliary interfaces |
rx_aux_sop | Input |
1 | |
rx_aux_valid | Input |
1 | |
rx_aux_data | Input |
72 | |
hdmi_tx_de | Output |
N | HDMI TX video interfaces
Note: N = symbols per clock
|
hdmi_tx_hsync | Output |
N | |
hdmi_tx_vsync | Output |
N | |
hdmi_tx_data | Output |
N*48 | |
tx_audio_format | Output |
5 | HDMI TX audio interfaces |
tx_audio_metadata | Output |
165 | |
tx_audio_info_ai | Output |
48 | |
tx_audio_CTS | Output |
20 | |
tx_audio_N | Output |
20 | |
tx_audio_de | Output |
1 | |
tx_audio_data | Output |
256 | |
tx_gcp | Output |
6 | HDMI TX sideband interfaces |
tx_info_avi | Output |
112 | |
tx_info_vsi | Output |
61 | |
tx_aux_eop | Output |
1 | HDMI TX auxiliary interfaces |
tx_aux_sop | Output |
1 | |
tx_aux_valid | Output |
1 | |
tx_aux_data | Output |
72 | |
tx_aux_ready | Output |
1 |
Signal | Direction | Width | Description |
---|---|---|---|
cpu_clk ( Intel® Quartus® Prime Standard Edition) | Input |
1 | CPU clock |
clock_bridge_0_in_clk_clk ( Intel® Quartus® Prime Pro Edition) | |||
cpu_clk_reset_n ( Intel® Quartus® Prime Standard Edition) | Input |
1 | CPU reset |
reset_bridge_0_reset_reset_n ( Intel® Quartus® Prime Pro Edition) | |||
tmds_bit_clock_ratio_pio_external_connection_export | Input |
1 | TMDS bit clock ratio |
measure_pio_external_connection_export | Input |
24 | Expected TMDS clock frequency |
measure_valid_pio_external_connection_export | Input |
1 | Indicates measure PIO is valid |
i2c_master_i2c_serial_sda_in ( Intel® Quartus® Prime Pro Edition) | Input |
1 | I2C Master interfaces |
i2c_master_i2c_serial_scl_in ( Intel® Quartus® Prime Pro Edition) | Input |
1 | |
i2c_master_i2c_serial_sda_oe ( Intel® Quartus® Prime Pro Edition) | Output |
1 | |
i2c_master_i2c_serial_scl_oe ( Intel® Quartus® Prime Pro Edition) | Output |
1 | |
i2c_master_ti_i2c_serial_sda_in ( Intel® Quartus® Prime Pro Edition) | Input |
1 | |
i2c_master_ti_i2c_serial_scl_in ( Intel® Quartus® Prime Pro Edition) | Input |
1 | |
i2c_master_ti_i2c_serial_sda_oe ( Intel® Quartus® Prime Pro Edition) | Output |
1 | |
i2c_master_ti_i2c_serial_scl_oe ( Intel® Quartus® Prime Pro Edition) | Output |
1 | |
oc_i2c_master_av_slave_translator_avalon_anti_slave_0_address ( Intel® Quartus® Prime Pro Edition) | Output | 3 | I2C Master Avalon® memory-mapped interfaces for DDC and SCDC |
oc_i2c_master_av_slave_translator_avalon_anti_slave_0_write ( Intel® Quartus® Prime Pro Edition) | Output | 1 | |
oc_i2c_master_av_slave_translator_avalon_anti_slave_0_readdata ( Intel® Quartus® Prime Pro Edition) | Input | 32 | |
oc_i2c_master_av_slave_translator_avalon_anti_slave_0_writedata ( Intel® Quartus® Prime Pro Edition) | Output | 32 | |
oc_i2c_master_av_slave_translator_avalon_anti_slave_0_waitrequest ( Intel® Quartus® Prime Pro Edition) | Input | 1 | |
oc_i2c_master_av_slave_translator_avalon_anti_slave_0_chipselect ( Intel® Quartus® Prime Pro Edition) | Output | 1 | |
oc_i2c_master_ti_avalon_anti_slave_address ( Intel® Quartus® Prime Standard Edition) | Output | 3 | I2C Master Avalon memory-mapped interfaces for Bitec daughter card revision 11, T1181 control |
oc_i2c_master_ti_avalon_anti_slave_write ( Intel® Quartus® Prime Standard Edition) | Output | 1 | |
oc_i2c_master_ti_avalon_anti_slave_readdata ( Intel® Quartus® Prime Standard Edition) | Input | 32 | |
oc_i2c_master_ti_avalon_anti_slave_writedata ( Intel® Quartus® Prime Standard Edition) | Output | 32 | |
oc_i2c_master_ti_avalon_anti_slave_waitrequest ( Intel® Quartus® Prime Standard Edition) | Input | 1 | |
oc_i2c_master_ti_avalon_anti_slave_chipselect ( Intel® Quartus® Prime Standard Edition) | Output | 1 | |
edid_ram_access_pio_external_connection_export | Output |
1 | EDID RAM access interfaces. Assert edid_ram_access_pio_external_connection_export when you want to write to or read from the EDID RAM on the RX top. Connect EDID RAM access Avalon-MM slave in Platform Designer to the EDID RAM interface on the top-level RX modules. |
edid_ram_slave_translator_address | Output |
8 | |
edid_ram_slave_translator_write | Output |
1 | |
edid_ram_slave_translator_read | Output |
1 | |
edid_ram_slave_translator_readdata | Input |
8 | |
edid_ram_slave_translator_writedata | Output |
8 | |
edid_ram_slave_translator_waitrequest | Input |
1 | |
powerup_cal_done_export ( Intel® Quartus® Prime Pro Edition) | Input | 1 | RX PMA Reconfiguration Avalon® memory-mapped interfaces |
rx_pma_cal_busy_export ( Intel® Quartus® Prime Pro Edition) | Input | 1 | |
rx_pma_ch_export ( Intel® Quartus® Prime Pro Edition) | Output | 2 | |
rx_pma_rcfg_mgmt_address ( Intel® Quartus® Prime Pro Edition) | Output | 12 | |
rx_pma_rcfg_mgmt_write ( Intel® Quartus® Prime Pro Edition) | Output | 1 | |
rx_pma_rcfg_mgmt_read ( Intel® Quartus® Prime Pro Edition) | Output | 1 | |
rx_pma_rcfg_mgmt_readdata ( Intel® Quartus® Prime Pro Edition) | Input | 32 | |
rx_pma_rcfg_mgmt_writedata ( Intel® Quartus® Prime Pro Edition) | Output | 32 | |
rx_pma_rcfg_mgmt_waitrequest ( Intel® Quartus® Prime Pro Edition) | Input | 1 | |
rx_pma_waitrequest_export ( Intel® Quartus® Prime Pro Edition) | Input | 1 | |
rx_rcfg_en_export ( Intel® Quartus® Prime Pro Edition) | Output | 1 | |
rx_rst_xcvr_export ( Intel® Quartus® Prime Pro Edition) | Output | 1 | |
tx_pll_rcfg_mgmt_translator_avalon_anti_slave_waitrequest | Input |
1 | TX PLL Reconfiguration Avalon® memory-mapped interfaces |
tx_pll_rcfg_mgmt_translator_avalon_anti_slave_writedata | Output |
32 | |
tx_pll_rcfg_mgmt_translator_avalon_anti_slave_address | Output |
10 |
|
tx_pll_rcfg_mgmt_translator_avalon_anti_slave_write | Output |
1 | |
tx_pll_rcfg_mgmt_translator_avalon_anti_slave_read | Output |
1 | |
tx_pll_rcfg_mgmt_translator_avalon_anti_slave_readdata | Input |
32 | |
tx_pll_waitrequest_pio_external_connection_export | Input |
1 | TX PLL waitrequest |
tx_pma_rcfg_mgmt_translator_avalon_anti_slave_address | Output |
12 |
TX PMA Reconfiguration Avalon® memory-mapped interfaces |
tx_pma_rcfg_mgmt_translator_avalon_anti_slave_write | Output |
1 | |
tx_pma_rcfg_mgmt_translator_avalon_anti_slave_read | Output |
1 | |
tx_pma_rcfg_mgmt_translator_avalon_anti_slave_readdata | Input |
32 | |
tx_pma_rcfg_mgmt_translator_avalon_anti_slave_writedata | Output |
32 | |
tx_pma_rcfg_mgmt_translator_avalon_anti_slave_waitrequest | Input |
1 | |
tx_pma_waitrequest_pio_external_connection_export | Input |
1 | TX PMA waitrequest |
tx_pma_cal_busy_pio_external_connection_export | Input |
1 | TX PMA Recalibration Busy |
tx_pma_ch_export | Output |
2 | TX PMA Channels |
tx_rcfg_en_pio_external_connection_export | Output |
1 | TX PMA Reconfiguration Enable |
tx_iopll_rcfg_mgmt_translator_avalon_anti_slave_writedata | Output |
32 | TX IOPLL Reconfiguration Avalon® memory-mapped interfaces |
tx_iopll_rcfg_mgmt_translator_avalon_anti_slave_readdata | Input |
32 | |
tx_iopll_rcfg_mgmt_translator_avalon_anti_slave_waitrequest | Input |
1 | |
tx_iopll_rcfg_mgmt_translator_avalon_anti_slave_address | Output |
9 | |
tx_iopll_rcfg_mgmt_translator_avalon_anti_slave_write | Output |
1 | |
tx_iopll_rcfg_mgmt_translator_avalon_anti_slave_read | Output |
1 | |
tx_os_pio_external_connection_export | Output |
2 |
Oversampling factor:
|
tx_rst_pll_pio_external_connection_export | Output |
1 | Reset to IOPLL and TX PLL |
tx_rst_xcvr_pio_external_connection_export | Output |
1 | Reset to TX Native PHY |
wd_timer_resetrequest_reset | Output |
1 | Watchdog timer reset |
color_depth_pio_external_connection_export | Input |
2 | Color depth |
tx_hpd_ack_pio_external_connection_export | Output |
1 | For TX hotplug detect handshaking |
tx_hpd_req_pio_external_connection_export | Input |
1 |