Visible to Intel only — GUID: qdk1476858314370
Ixiasoft
Visible to Intel only — GUID: qdk1476858314370
Ixiasoft
3.6. Clocking Scheme
Clock | Signal Name in Design | Description | ||||||||||||||||
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TX IOPLL/ TX PLL Reference Clock 1 | hdmi_clk_in | Reference clock to the TX IOPLL and TX PLL. The clock frequency is the same as the expected TMDS clock frequency from the HDMI TX TMDS clock channel. For this HDMI Intel® FPGA IP design example, this clock is connected to the RX TMDS clock for demonstration purpose. In your application, you need to supply a dedicated clock with TMDS clock frequency from a programmable oscillator for better jitter performance.
Note: Do not use a transceiver RX pin as a TX PLL reference clock. Your design will fail to fit if you place the HDMI TX refclk on an RX pin.
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TX Transceiver Clock Out | tx_clk | Clock out recovered from the transceiver, and the frequency varies depending on the data rate and symbols per clock. TX transceiver clock out frequency = Transceiver data rate/ (Symbol per clock*10) |
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TX PLL Serial Clock | tx_bonding_clocks | Serial fast clock generated by TX PLL. The clock frequency is set based on the data rate. |
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TX/RX Link Speed Clock | ls_clk | Link speed clock. The link speed clock frequency depends on the expected TMDS clock frequency, oversampling factor, symbols per clock, and TMDS bit clock ratio.
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TX/RX Video Clock | vid_clk |
Video data clock. The video data clock frequency is derived from the TX link speed clock based on the color depth.
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RX TMDS Clock | tmds_clk_in | TMDS clock channel from the HDMI RX and connects to the reference clock to the IOPLL. |
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RX CDR Reference Clock 0 /TX PLL Reference Clock 0 | fr_clk | Free running reference clock to RX CDR and TX PLL. This clock is required for power-up calibration. |
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RX CDR Reference Clock 1 | iopll_outclk0 | Reference clock to the RX CDR of RX transceiver.
Note: Do not use a transceiver RX pin as a CDR reference clock. Your design will fail to fit if you place the HDMI RX refclk on an RX pin.
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RX Transceiver Clock Out | rx_clk | Clock out recovered from the transceiver, and the frequency varies depending on the data rate and symbols per clock. RX transceiver clock out frequency = Transceiver data rate/ (Symbol per clock*10) |
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Management Clock | mgmt_clk |
A free running 100 MHz clock for these components:
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I2C Clock | i2c_clk | A 100 MHz clock input that clocks I2C slave, SCDC registers in the HDMI RX core, and EDID RAM. |