HDMI Intel® Arria 10 FPGA IP Design Example User Guide

ID 683156
Date 11/12/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.3. Directory Structure

The directories contain the generated files for the HDMI Intel® FPGA IP design example.
Figure 22. Directory Structure for the Design Example
Table 29.  Generated RTL Files
Folders Files
gxb
  • /gxb_rx.qsys ( Intel® Quartus® Prime Standard Edition)
  • /gxb_rx.ip ( Intel® Quartus® Prime Pro Edition)
  • /gxb_rx_reset.qsys ( Intel® Quartus® Prime Standard Edition)
  • /gxb_rx_reset.ip ( Intel® Quartus® Prime Pro Edition)
  • /gxb_tx.qsys ( Intel® Quartus® Prime Standard Edition)
  • /gxb_tx.ip ( Intel® Quartus® Prime Pro Edition)
  • /gxb_tx_fpll.qsys ( Intel® Quartus® Prime Standard Edition)
  • /gxb_tx_fpll.ip ( Intel® Quartus® Prime Pro Edition)
  • /gxb_tx_reset.qsys ( Intel® Quartus® Prime Standard Edition)
  • /gxb_tx_reset.ip ( Intel® Quartus® Prime Pro Edition)
hdmi_rx
  • /hdmi_rx.qsys ( Intel® Quartus® Prime Standard Edition)
  • /hdmi_rx.ip ( Intel® Quartus® Prime Pro Edition)
/hdmi_rx_top.v
/mr_clock_sync.v ( Intel® Quartus® Prime Standard Edition)
/mr_hdmi_rx_core_top.v ( Intel® Quartus® Prime Standard Edition)
/mr_rx_oversample.v ( Intel® Quartus® Prime Standard Edition)
/symbol_aligner.v
Panasonic.hex ( Intel® Quartus® Prime Pro Edition)
hdmi_tx
  • /hdmi_tx.qsys ( Intel® Quartus® Prime Standard Edition)
  • /hdmi_tx.ip ( Intel® Quartus® Prime Pro Edition)
/hdmi_tx_top.v
/mr_ce.v ( Intel® Quartus® Prime Standard Edition)
/mr_hdmi_tx_core_top.v ( Intel® Quartus® Prime Standard Edition)
/mr_tx_oversample.v ( Intel® Quartus® Prime Standard Edition)
i2c_master

( Intel® Quartus® Prime Standard Edition)

/i2c_master_bit_ctrl.v
/i2c_master_byte_ctrl.v
/i2c_master_defines.v
/i2c_master_top.v
/oc_i2c_master.v
/oc_i2c_master_hw.tcl
/timescale.v
i2c_slave /edid_ram.qsys ( Intel® Quartus® Prime Standard Edition)
/Panasonic.hex ( Intel® Quartus® Prime Standard Edition)
/i2c_avl_mst_intf_gen.v
/i2c_clk_cnt.v
/i2c_condt_det.v
/i2c_databuffer.v
/i2c_rxshifter.v
/i2c_slvfsm.v
/i2c_spksupp.v
/i2c_txout.v
/i2c_txshifter.v
/i2cslave_to_avlmm_bridge.v
pll
  • /pll_hdmi.qsys ( Intel® Quartus® Prime Standard Edition)
  • /pll_hdmi.ip ( Intel® Quartus® Prime Pro Edition)
  • /pll_hdmi_reconfig.qsys ( Intel® Quartus® Prime Standard Edition)
  • /pll_hdmi_reconfig.ip ( Intel® Quartus® Prime Pro Edition)
quartus.ini
common
  • /clock_control.qsys ( Intel® Quartus® Prime Standard Edition)
  • /clock_control.ip ( Intel® Quartus® Prime Pro Edition)
  • /fifo.qsys ( Intel® Quartus® Prime Standard Edition)
  • /fifo.ip ( Intel® Quartus® Prime Pro Edition)
  • /output_buf_i2c.qsys ( Intel® Quartus® Prime Standard Edition)
  • /output_buf_i2c.ip ( Intel® Quartus® Prime Pro Edition)
/reset_controller.qsys ( Intel® Quartus® Prime Standard Edition)
/clock_crosser.v
dcfifo_inst.v
debouncer.sv ( Intel® Quartus® Prime Pro Edition)
hdr /altera_hdmi_aux_hdr.v
/altera_hdmi_aux_snk.v
/altera_hdmi_aux_src.v
/altera_hdmi_hdr_infoframe.v
/avalon_st_mutiplexer.qsys
reconfig_mgmt /mr_compare_pll.v
/mr_compare_rx.v
/mr_rate_detect.v
/mr_reconfig_master_pll.v
/mr_reconfig_master_rx.v
/mr_reconfig_mgmt.v
/mr_rom_pll_dprioaddr.v
/mr_rom_pll_valuemask_8bpc.v
/mr_rom_pll_valuemask_10bpc.v
/mr_rom_pll_valuemask_12bpc.v
/mr_rom_pll_valuemask_16bpc.v
/mr_rom_rx_dprioaddr_bitmask.v
/mr_rom_rx_valuemask.v
/mr_state_machine.v
sdc /a10_hdmi2.sdc
/mr_reconfig_mgmt.sdc
/jtag.sdc
/rxtx_link.sdc
/mr_clock_sync.sdc ( Intel® Quartus® Prime Standard Edition)
Table 30.   Generated Simulation FilesRefer to the Simulation Testbench section for more information.
Folders Files
aldec /aldec.do
/rivierapro_setup.tcl
cadence /cds.lib
/hdl.var
<cds_libs folder>
mentor /mentor.do
/msim_setup.tcl
synopsys /vcs/filelist.f
/vcs/vcs_setup.sh
/vcs/vcs_sim.sh
/vcsmx/vcsmx_setup.sh
/vcsmx/vcsmx_sim.sh
/vcsmx/synopsys_sim_setup
xcelium

( Intel® Quartus® Prime Pro Edition)

/cds.lib
/hdl.var
/xcelium_setup.sh
/xcelium_sim.sh
<cds_libs folder>
common

( Intel® Quartus® Prime Pro Edition)

/modelsim_files.tcl
/riviera_files.tcl
/vcs_files.tcl
/vcsmx_files.tcl
/xcelium_files.tcl
hdmi_rx
  • /hdmi_rx.qsys ( Intel® Quartus® Prime Standard Edition)
  • /hdmi_rx.ip ( Intel® Quartus® Prime Pro Edition)
/hdmi_rx.sopcinfo ( Intel® Quartus® Prime Standard Edition)
/Panasonic.hex ( Intel® Quartus® Prime Pro Edition)
/symbol_aligner.v ( Intel® Quartus® Prime Pro Edition)
hdmi_tx
  • /hdmi_tx.qsys ( Intel® Quartus® Prime Standard Edition)
  • /hdmi_tx.ip ( Intel® Quartus® Prime Pro Edition)
/hdmi_tx.sopcinfo ( Intel® Quartus® Prime Standard Edition)
Table 31.  Generated Software Files
Folders Files
tx_control_src
Note: The tx_control folder also contains duplicates of these files.
/intel_fpga_i2c.c ( Intel® Quartus® Prime Pro Edition)
/intel_fpga_i2c.h ( Intel® Quartus® Prime Pro Edition)
/i2c.c ( Intel® Quartus® Prime Standard Edition)
/i2c.h ( Intel® Quartus® Prime Standard Edition)
/main.c
/xcvr_gpll_rcfg.c
/xcvr_gpll_rcfg.h
/ti_i2c.c ( Intel® Quartus® Prime Standard Edition)
/ti_i2c.h ( Intel® Quartus® Prime Standard Edition)