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1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. HDMI 2.0 Design Example (Support FRL = 0)
4. HDCP Over HDMI 2.0/2.1 Design Example
5. HDMI Intel® Arria® 10 FPGA IP Design Example User Guide Archives
6. Revision History for HDMI Intel® Arria® 10 FPGA IP Design Example User Guide
2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram
2.2. Creating RX-Only or TX-Only Designs
2.3. Hardware and Software Requirements
2.4. Directory Structure
2.5. Design Components
2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
2.7. Design Software Flow
2.8. Running the Design in Different FRL Rates
2.9. Clocking Scheme
2.10. Interface Signals
2.11. Design RTL Parameters
2.12. Hardware Setup
2.13. Simulation Testbench
2.14. Design Limitations
2.15. Debugging Features
2.16. Upgrading Your Design
3.1. HDMI 2.0 RX-TX Retransmit Design Block Diagram
3.2. Hardware and Software Requirements
3.3. Directory Structure
3.4. Design Components
3.5. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
3.6. Clocking Scheme
3.7. Interface Signals
3.8. Design RTL Parameters
3.9. Hardware Setup
3.10. Simulation Testbench
3.11. Upgrading Your Design
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3.2. Hardware and Software Requirements
Intel uses the following hardware and software to test the design example.
Hardware
- Intel® Arria® 10 GX FPGA Development Kit
- HDMI Source (Graphics Processor Unit (GPU))
- HDMI Sink (Monitor)
- Bitec HDMI FMC 2.0 daughter card (Revision 11)
- HDMI cables
Note: You can select the revision of the Bitec HDMI daughter card by setting the local parameter BITEC_DAUGHTER_CARD_REV to 4, 6, or 11 in the top-level file ( a10_hdmi2_demo.v ). When you change the revision, the design may swap the transceiver channels and invert the polarity according to the Bitec HDMI daughter card requirements. If you set the BITEC_DAUGHTER_CARD_REV parameter to 0, the design does not make any changes to the transceiver channels and the polarity.
Software
- Intel® Quartus® Prime version 18.1 and later (for hardware testing)
- ModelSim* - Intel® FPGA Edition, ModelSim* - Intel® FPGA Starter Edition, , Riviera-PRO* , VCS* (Verilog HDL only)/ VCS* MX, or Xcelium* Parallel simulator