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1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. HDMI 2.0 Design Example (Support FRL = 0)
4. HDCP Over HDMI 2.0/2.1 Design Example
5. HDMI Intel® Arria® 10 FPGA IP Design Example User Guide Archives
6. Revision History for HDMI Intel® Arria® 10 FPGA IP Design Example User Guide
2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram
2.2. Creating RX-Only or TX-Only Designs
2.3. Hardware and Software Requirements
2.4. Directory Structure
2.5. Design Components
2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
2.7. Design Software Flow
2.8. Running the Design in Different FRL Rates
2.9. Clocking Scheme
2.10. Interface Signals
2.11. Design RTL Parameters
2.12. Hardware Setup
2.13. Simulation Testbench
2.14. Design Limitations
2.15. Debugging Features
2.16. Upgrading Your Design
Features
3.1. HDMI 2.0 RX-TX Retransmit Design Block Diagram
3.2. Hardware and Software Requirements
3.3. Directory Structure
3.4. Design Components
3.5. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
3.6. Clocking Scheme
3.7. Interface Signals
3.8. Design RTL Parameters
3.9. Hardware Setup
3.10. Simulation Testbench
3.11. Upgrading Your Design
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3. HDMI 2.0 Design Example (Support FRL = 0)
The HDMI Intel® FPGA IP design example demonstrates one HDMI instance parallel loopback comprising three RX channels and four TX channels.
Design Example | Data Rate | Channel Mode | Loopback Type |
---|---|---|---|
Arria 10 HDMI RX-TX Retransmit |
< 6,000 Mbps | Simplex | Parallel with FIFO buffer |
Features
- The design instantiates FIFO buffers to perform a direct HDMI video stream passthrough between the HDMI sink and source.
- The design uses LED status for early debugging stage.
- The design comes with RX and TX only options.
- The design demonstrates the insertion and filtering of Dynamic Range and Mastering (HDR) InfoFrame in RX-TX link module.
- The design demonstrates the management of EDID passthrough from an external HDMI sink to an external HDMI source when triggered by a TX hot-plug event.
- The design allows run-time control through DIP switch and push-button to manage the HDMI TX core signals:
- mode signal to select DVI or HDMI encoded video frame
- info_avi[47], info_vsi[61], and audio_info_ai[48] signals to select auxiliary packet transmission through sidebands or auxiliary data ports
The RX instance receives a video source from the external video generator, and the data then goes through a loopback FIFO before it is transmitted to the TX instance. You need to connect an external video analyzer, monitor, or a television with HDMI connection to the TX core to verify the functionality.
- HDMI 2.0 RX-TX Retransmit Design Block Diagram
- Hardware and Software Requirements
- Directory Structure
- Design Components
- Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
- Clocking Scheme
- Interface Signals
- Design RTL Parameters
- Hardware Setup
- Simulation Testbench
- Upgrading Your Design