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1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. HDMI 2.0 Design Example (Support FRL = 0)
4. HDCP Over HDMI 2.0/2.1 Design Example
5. HDMI Intel® Arria® 10 FPGA IP Design Example User Guide Archives
6. Revision History for HDMI Intel® Arria® 10 FPGA IP Design Example User Guide
2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram
2.2. Creating RX-Only or TX-Only Designs
2.3. Hardware and Software Requirements
2.4. Directory Structure
2.5. Design Components
2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
2.7. Design Software Flow
2.8. Running the Design in Different FRL Rates
2.9. Clocking Scheme
2.10. Interface Signals
2.11. Design RTL Parameters
2.12. Hardware Setup
2.13. Simulation Testbench
2.14. Design Limitations
2.15. Debugging Features
2.16. Upgrading Your Design
3.1. HDMI 2.0 RX-TX Retransmit Design Block Diagram
3.2. Hardware and Software Requirements
3.3. Directory Structure
3.4. Design Components
3.5. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
3.6. Clocking Scheme
3.7. Interface Signals
3.8. Design RTL Parameters
3.9. Hardware Setup
3.10. Simulation Testbench
3.11. Upgrading Your Design
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2.11. Design RTL Parameters
Use the HDMI TX and RX Top RTL parameters to customize the design example.
Most of the design parameters are available in the Design Example tab of the HDMI Intel® FPGA IP parameter editor. You can still change the design example settings you made in the parameter editor through the RTL parameters.
Parameter | Value | Description |
---|---|---|
SUPPORT_DEEP_COLOR |
|
Determines if the core can encode deep color formats. |
SUPPORT_AUXILIARY |
|
Determines if the auxiliary channel encoding is included. |
SYMBOLS_PER_CLOCK | 8 | Supports 8 symbols per clock for Intel® Arria® 10 devices. |
SUPPORT_AUDIO |
|
Determines if the core can encode audio. |
EDID_RAM_ADDR_WIDTH | 8 (Default value) | Log base 2 of the EDID RAM size. |
BITEC_DAUGHTER_CARD_REV |
|
Specifies the revision of the Bitec HDMI daughter card used. When you change the revision, the design may swap the transceiver channels and invert the polarity according to the Bitec HDMI daughter card requirements. If you set the BITEC_DAUGHTER_CARD_REV parameter to 0, the design does not make any changes to the transceiver channels and the polarity. |
POLARITY_INVERSION |
|
Set this parameter to 1 to invert the value of each bit of the input data. Setting this parameter to 1 assigns 4'b1111 to the rx_polinv port of the RX transceiver. |
Parameter | Value | Description |
---|---|---|
USE_FPLL | 1 | Supports fPLL as TX PLL only for Intel® Arria® 10 devices. Always set this parameter to 1. |
SUPPORT_DEEP_COLOR |
|
Determines if the core can encode deep color formats. |
SUPPORT_AUXILIARY |
|
Determines if the auxiliary channel encoding is included. |
SYMBOLS_PER_CLOCK | 8 | Supports 8 symbols per clock for Intel® Arria® 10 devices. |
SUPPORT_AUDIO |
|
Determines if the core can encode audio. |
BITEC_DAUGHTER_CARD_REV |
|
Specifies the revision of the Bitec HDMI daughter card used. When you change the revision, the design may swap the transceiver channels and invert the polarity according to the Bitec HDMI daughter card requirements. If you set the BITEC_DAUGHTER_CARD_REV parameter to 0, the design does not make any changes to the transceiver channels and the polarity. |
POLARITY_INVERSION |
|
Set this parameter to 1 to invert the value of each bit of the input data. Setting this parameter to 1 assigns 4'b1111 to the tx_polinv port of the TX transceiver. |