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1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. HDMI 2.0 Design Example (Support FRL = 0)
4. HDCP Over HDMI 2.0/2.1 Design Example
5. HDMI Intel® Arria® 10 FPGA IP Design Example User Guide Archives
6. Revision History for HDMI Intel® Arria® 10 FPGA IP Design Example User Guide
2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram
2.2. Creating RX-Only or TX-Only Designs
2.3. Hardware and Software Requirements
2.4. Directory Structure
2.5. Design Components
2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
2.7. Design Software Flow
2.8. Running the Design in Different FRL Rates
2.9. Clocking Scheme
2.10. Interface Signals
2.11. Design RTL Parameters
2.12. Hardware Setup
2.13. Simulation Testbench
2.14. Design Limitations
2.15. Debugging Features
2.16. Upgrading Your Design
3.1. HDMI 2.0 RX-TX Retransmit Design Block Diagram
3.2. Hardware and Software Requirements
3.3. Directory Structure
3.4. Design Components
3.5. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
3.6. Clocking Scheme
3.7. Interface Signals
3.8. Design RTL Parameters
3.9. Hardware Setup
3.10. Simulation Testbench
3.11. Upgrading Your Design
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1.4. HDMI Intel® FPGA IP Design Example Parameters
Parameter |
Value |
Description |
---|---|---|
Available Design Example |
||
Select Design | Arria 10 HDMI RX-TX Retransmit |
Select the design example to be generated. |
Design Example Files | ||
Simulation | On, Off | Turn on this option to generate the necessary files for the simulation testbench. |
Synthesis | On, Off | Turn on this option to generate the necessary files for Intel® Quartus® Prime compilation and hardware demonstration. |
Generated HDL Format |
||
Generate File Format | Verilog, VHDL | Select your preferred HDL format for the generated design example fileset.
Note: This option only determines the format for the generated top level IP files. All other files (e.g. example testbenches and top level files for hardware demonstration) are in Verilog HDL format.
|
Target Development Kit |
||
Select Board | No Development Kit, Arria 10 GX FPGA Development Kit, Custom Development Kit |
Select the board for the targeted design example.
|
Target Device | ||
Change Target Device | On, Off | Turn on this option and select the preferred device variant for the development kit. |