3.4. Design Components
Module | Description |
---|---|
HDMI RX Core | The IP receives the serial data from the Transceiver Native PHY and performs data alignment, channel deskew, TMDS decoding, auxiliary data decoding, video data decoding, audio data decoding, and descrambling. |
I2C |
I2C is the interface used for Sink Display Data Channel (DDC) and Status and Data Channel (SCDC). The HDMI source uses the DDC to determine the capabilities and characteristics of the sink by reading the Enhanced Extended Display Identification Data (E-EDID) data structure.
|
EDID RAM | The design stores the EDID information using the RAM 1-port IP core. A standard two-wire (clock and data) serial bus protocol (I2C slave-only controller) transfers the CEA-861-D Compliant E-EDID data structure. This EDID RAM stores the E-EDID information.
Note: If you turn on the Include EDID RAM parameter, this block will be included inside the core and will not be visible at this level.
|
IOPLL | The IOPLL generates the RX CDR reference clock, link speed clock, and video clock for the incoming TMDS clock.
Note: The default IOPLL configuration is not valid for any HDMI resolution. The IOPLL is reconfigured to the appropriate settings upon power up.
|
Transceiver PHY Reset Controller | The Transceiver PHY reset controller ensures a reliable initialization of the RX transceivers. The reset input of this controller is triggered by the RX reconfiguration, and it generates the corresponding analog and digital reset signal to the Transceiver Native PHY block according to the reset sequencing inside the block. |
RX Native PHY | Hard transceiver block that receives the serial data from an external video source. It deserializes the serial data to parallel data before passing the data to the HDMI RX core. |
RX Reconfiguration Management | RX reconfiguration management that implements rate detection circuitry with the HDMI PLL to drive the RX transceiver to operate at any arbitrary link rates ranging from 250 Mbps to 6,000 Mbps. |
IOPLL Reconfiguration | IOPLL reconfiguration block facilitates dynamic real-time reconfiguration of PLLs in Intel FPGAs. This block updates the output clock frequency and PLL bandwidth in real time, without reconfiguring the entire FPGA. This block runs at 100 MHz in Intel® Arria® 10 devices. Due to IOPLL reconfiguration limitation, apply the Quartus INI permit_nf_pll_reconfig_out_of_lock=on during the IOPLL reconfiguration IP generation. To apply the Quartus INI, include “permit_nf_pll_reconfig_out_of_lock=on” in the quartus.ini file and place in the file the Intel® Quartus® Prime project directory. You should see a warning message when you edit the IOPLL reconfiguration block (pll_hdmi_reconfig) in the Quartus Prime software with the INI.
Note: Without this Quartus INI, IOPLL reconfiguration cannot be completed if the IOPLL loses lock during reconfiguration.
|
PIO | The parallel input/output (PIO) block functions as control, status and reset interfaces to or from the CPU sub-system. |
Module | Description |
---|---|
HDMI TX Core | The IP core receives video data from the top level and performs TMDS encoding, auxiliary data encoding, audio data encoding, video data encoding, and scrambling. |
I2C Master |
I2C is the interface used for Sink Display Data Channel (DDC) and Status and Data Channel (SCDC). The HDMI source uses the DDC to determine the capabilities and characteristics of the sink by reading the Enhanced Extended Display Identification Data (E-EDID) data structure.
|
IOPLL | The IOPLL supplies the link speed clock and video clock from the incoming TMDS clock.
Note: The default IOPLL configuration is not valid for any HDMI resolution. The IOPLL is reconfigured to the appropriate settings upon power up.
|
Transceiver PHY Reset Controller | The Transceiver PHY reset controller ensures a reliable initialization of the TX transceivers. The reset input of this controller is triggered from the top level, and it generates the corresponding analog and digital reset signal to the Transceiver Native PHY block according to the reset sequencing inside the block. The tx_ready output signal from this block also functions as a reset signal to the HDMI Intel® FPGA IP to indicate the transceiver is up and running, and ready to receive data from the core. |
Transceiver Native PHY | Hard transceiver block that receives the parallel data from the HDMI TX core and serializes the data from transmitting it. Reconfiguration interface is enabled in the TX Native PHY block to demonstrate the connection between TX Native PHY and transceiver arbiter. No reconfiguration is performed for TX Native PHY.
Note: To meet the HDMI TX inter-channel skew requirement, set the TX channel bonding mode option in the Intel® Arria® 10 Transceiver Native PHY parameter editor to PMA and PCS bonding. You also need to add the maximum skew (set_max_skew) constraint requirement to the digital reset signal from the transceiver reset controller (tx_digitalreset) as recommended in the Intel® Arria® 10 Transceiver PHY User Guide.
|
TX PLL | The transmitter PLL block provides the serial fast clock to the Transceiver Native PHY block. For this HDMI Intel® FPGA IP design example, fPLL is used as TX PLL. |
IOPLL Reconfiguration | IOPLL reconfiguration block facilitates dynamic real-time reconfiguration of PLLs in Intel FPGAs. This block updates the output clock frequency and PLL bandwidth in real time, without reconfiguring the entire FPGA. This block runs at 100 MHz in Intel® Arria® 10 devices. Due to IOPLL reconfiguration limitation, apply the Quartus INI permit_nf_pll_reconfig_out_of_lock=on during the IOPLL reconfiguration IP generation. To apply the Quartus INI, include “permit_nf_pll_reconfig_out_of_lock=on” in the quartus.ini file and place in the file the Intel® Quartus® Prime project directory. You should see a warning message when you edit the IOPLL reconfiguration block (pll_hdmi_reconfig) in the Intel® Quartus® Prime software with the INI.
Note: Without this Quartus INI, IOPLL reconfiguration cannot be completed if the IOPLL loses lock during reconfiguration.
|
PIO | The parallel input/output (PIO) block functions as control, status and reset interfaces to or from the CPU sub-system. |
TMDS Clock Frequency (MHz) | TMDS Bit clock Ratio | Oversampling Factor | Transceiver Data Rate (Mbps) |
---|---|---|---|
85–150 | 1 | Not applicable | 3400–6000 |
100–340 | 0 | Not applicable | 1000–3400 |
50–100 | 0 | 5 | 2500–5000 |
35–50 | 0 | 3 | 1050–1500 |
30–35 | 0 | 4 | 1200–1400 |
25–30 | 0 | 5 | 1250–1500 |