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1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. HDMI 2.0 Design Example (Support FRL = 0)
4. HDCP Over HDMI 2.0/2.1 Design Example
5. HDMI Intel® Arria® 10 FPGA IP Design Example User Guide Archives
6. Revision History for HDMI Intel® Arria® 10 FPGA IP Design Example User Guide
2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram
2.2. Creating RX-Only or TX-Only Designs
2.3. Hardware and Software Requirements
2.4. Directory Structure
2.5. Design Components
2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
2.7. Design Software Flow
2.8. Running the Design in Different FRL Rates
2.9. Clocking Scheme
2.10. Interface Signals
2.11. Design RTL Parameters
2.12. Hardware Setup
2.13. Simulation Testbench
2.14. Design Limitations
2.15. Debugging Features
2.16. Upgrading Your Design
3.1. HDMI 2.0 RX-TX Retransmit Design Block Diagram
3.2. Hardware and Software Requirements
3.3. Directory Structure
3.4. Design Components
3.5. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
3.6. Clocking Scheme
3.7. Interface Signals
3.8. Design RTL Parameters
3.9. Hardware Setup
3.10. Simulation Testbench
3.11. Upgrading Your Design
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2.15.3. Clock Frequency Measurement
Use this feature to check the frequency for the different clocks.
- In the hdmi_rx_top and hdmi_tx_top files, uncomment “//`define DEBUG_EN 1”.
- Add the refclock_measure signal from each mr_rate_detect instance to the Signal Tap Logic Analyzer to get the clock frequency of each clock (in 10 ms duration).
- Compile the design with Signal Tap Logic Analyzer.
- Program the SOF file and run the Signal Tap Logic Analyzer.
Module | mr_rate_detect Instance | Clock to be Measured |
---|---|---|
hdmi_rx_top | rx_pll_tmds | RX CDR reference clock 0 |
rx_clk0_freq | RX transceiver clock out from channel 0 | |
rx_vid_clk_freq | RX video clock | |
rx_frl_clk_freq | RX FRL clock | |
rx_hsync_freq | Hsync frequency of the received video frame | |
hdmi_tx_top | tx_clk0_freq | TX transceiver clock out from channel 0 |
vid_clk_freq | TX video clock | |
frl_clk_freq | TX FRL clock | |
tx_hsync_freq | Hsync frequency of the video frame to be transmitted |