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1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. HDMI 2.0 Design Example (Support FRL = 0)
4. HDCP Over HDMI 2.0/2.1 Design Example
5. HDMI Intel® Arria® 10 FPGA IP Design Example User Guide Archives
6. Revision History for HDMI Intel® Arria® 10 FPGA IP Design Example User Guide
2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram
2.2. Creating RX-Only or TX-Only Designs
2.3. Hardware and Software Requirements
2.4. Directory Structure
2.5. Design Components
2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
2.7. Design Software Flow
2.8. Running the Design in Different FRL Rates
2.9. Clocking Scheme
2.10. Interface Signals
2.11. Design RTL Parameters
2.12. Hardware Setup
2.13. Simulation Testbench
2.14. Design Limitations
2.15. Debugging Features
2.16. Upgrading Your Design
3.1. HDMI 2.0 RX-TX Retransmit Design Block Diagram
3.2. Hardware and Software Requirements
3.3. Directory Structure
3.4. Design Components
3.5. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
3.6. Clocking Scheme
3.7. Interface Signals
3.8. Design RTL Parameters
3.9. Hardware Setup
3.10. Simulation Testbench
3.11. Upgrading Your Design
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4.3.5.1. Push Buttons and LED Functions
Use the push buttons and LED functions on the board to control your demonstration.
Push Button/LED | Functions |
---|---|
cpu_resetn | Press once to perform system reset. |
user_pb[0] | Press once to toggle the HPD signal to the standard HDMI source. |
user_pb[1] |
|
user_pb[2] |
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user_led[0] |
RX HDMI PLL lock status.
|
user_led[1] |
RX HDMI core lock status
|
user_led[2] |
RX HDCP1x IP decryption status.
|
user_led[3] |
RX HDCP2x IP decryption status.
|
user_led[4] |
TX HDMI PLL lock status.
|
user_led[5] |
TX transceiver PLL lock status.
|
user_led[6] |
TX HDCP1x IP encryption status.
|
user_led[7] |
TX HDCP2x IP encryption status.
|
Push Button/LED | Functions | |
---|---|---|
cpu_resetn | Press once to perform system reset. | |
user_dipsw | User-defined DIP switch to toggle the passthrough mode.
Refer to Running the Design in Different FRL Rates for more information about setting the different FRL rates. |
|
user_pb[0] | Press once to toggle the HPD signal to the standard HDMI source. | |
user_pb[1] | Reserved. | |
user_pb[2] | Press once to read the SCDC registers from the sink connected to the TX of the Bitec HDMI 2.1 FMC daughter card.
Note: To enable read, you must set DEBUG_MODE to 1 in the software.
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user_led_g[0] | RX FRL clock PLL lock status.
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user_led_g[1] | RX HDMI video lock status.
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user_led_g[2] | RX HDCP1x IP decryption status.
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user_led_g[3] | RX HDCP2x IP decryption status.
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user_led_g[4] | TX FRL clock PLL lock status.
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user_led_g[5] | TX HDMI video lock status.
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user_led_g[6] | TX HDCP1x IP encryption status.
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user_led_g[7] |
TX HDCP2x IP encryption status.
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