Visible to Intel only — GUID: gpr1476763567315
Ixiasoft
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. HDMI 2.0 Design Example (Support FRL = 0)
4. HDCP Over HDMI 2.0/2.1 Design Example
5. HDMI Intel® Arria® 10 FPGA IP Design Example User Guide Archives
6. Revision History for HDMI Intel® Arria® 10 FPGA IP Design Example User Guide
2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram
2.2. Creating RX-Only or TX-Only Designs
2.3. Hardware and Software Requirements
2.4. Directory Structure
2.5. Design Components
2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
2.7. Design Software Flow
2.8. Running the Design in Different FRL Rates
2.9. Clocking Scheme
2.10. Interface Signals
2.11. Design RTL Parameters
2.12. Hardware Setup
2.13. Simulation Testbench
2.14. Design Limitations
2.15. Debugging Features
2.16. Upgrading Your Design
3.1. HDMI 2.0 RX-TX Retransmit Design Block Diagram
3.2. Hardware and Software Requirements
3.3. Directory Structure
3.4. Design Components
3.5. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
3.6. Clocking Scheme
3.7. Interface Signals
3.8. Design RTL Parameters
3.9. Hardware Setup
3.10. Simulation Testbench
3.11. Upgrading Your Design
Visible to Intel only — GUID: gpr1476763567315
Ixiasoft
1.2. Simulating the Design
The HDMI testbench simulates a serial loopback design from a TX instance to an RX instance. Internal video pattern generator, audio sample generator, sideband data generator, and auxiliary data generator modules drive the HDMI TX instance and the serial output from the TX instance connects to the RX instance in the testbench.
Figure 3. Design Simulation Flow
- Go to the desired simulation folder.
- Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator.
- Analyze the results.
Table 1. Steps to Run Simulation Simulator Working Directory Instructions Riviera-PRO* /simulation/aldec In the command line, typevsim -c -do aldec.do
ModelSim* /simulation/mentor In the command line, typevsim -c -do mentor.do
VCS* /simulation/synopsys/vcs In the command line, typesource vcs_sim.sh
VCS* MX /simulation/synopsys/vcsmx In the command line, typesource vcsmx_sim.sh
Xcelium* Parallel /simulation/xcelium In the command line, type source xcelium_sim.sh
A successful simulation ends with the following message:# SYMBOLS_PER_CLOCK = 2 # VIC = 4 # FRL_RATE = 0 # BPP = 0 # AUDIO_FREQUENCY (kHz) = 48 # AUDIO_CHANNEL = 8 # Simulation pass