HDMI Intel® Arria 10 FPGA IP Design Example User Guide

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ID 683156
Date 11/12/2021
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices 2. HDMI 2.1 Design Example (Support FRL = 1) 3. HDMI 2.0 Design Example (Support FRL = 0) 4. HDCP Over HDMI 2.0/2.1 Design Example 5. HDMI Intel® Arria® 10 FPGA IP Design Example User Guide Archives 6. Revision History for HDMI Intel® Arria® 10 FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices x
1.1. Generating the Design 1.2. Simulating the Design 1.3. Compiling and Testing the Design 1.4. HDMI Intel® FPGA IP Design Example Parameters
2. HDMI 2.1 Design Example (Support FRL = 1) x
2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.2. Creating RX-Only or TX-Only Designs 2.3. Hardware and Software Requirements 2.4. Directory Structure 2.5. Design Components 2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 2.7. Design Software Flow 2.8. Running the Design in Different FRL Rates 2.9. Clocking Scheme 2.10. Interface Signals 2.11. Design RTL Parameters 2.12. Hardware Setup 2.13. Simulation Testbench 2.14. Design Limitations 2.15. Debugging Features 2.16. Upgrading Your Design
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.15. Debugging Features x
2.15.1. Software Debugging Message 2.15.2. SCDC Information from the Sink Connected to TX 2.15.3. Clock Frequency Measurement
3. HDMI 2.0 Design Example (Support FRL = 0) x
3.1. HDMI 2.0 RX-TX Retransmit Design Block Diagram 3.2. Hardware and Software Requirements 3.3. Directory Structure 3.4. Design Components 3.5. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 3.6. Clocking Scheme 3.7. Interface Signals 3.8. Design RTL Parameters 3.9. Hardware Setup 3.10. Simulation Testbench 3.11. Upgrading Your Design
4. HDCP Over HDMI 2.0/2.1 Design Example x
4.1. High-bandwidth Digital Content Protection (HDCP) 4.2. Nios II Processor Software Flow 4.3. Design Walkthrough 4.4. Protection of Encryption Key Embedded in FPGA Design 4.5. Security Considerations 4.6. Debug Guidelines
4.1. High-bandwidth Digital Content Protection (HDCP) x
4.1.1. HDCP Over HDMI Design Example Architecture
4.3. Design Walkthrough x
4.3.1. Set Up the Hardware 4.3.2. Generate the Design 4.3.3. Include HDCP Production Keys 4.3.4. Compile the Design 4.3.5. View the Results
4.3.3. Include HDCP Production Keys x
4.3.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) 4.3.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
4.3.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) x
4.3.3.1.1. HDCP Key Mapping from DCP Key Files 4.3.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 4.3.3.1.3. hdcp2x_rx_kmem.v file 4.3.3.1.4. hdcp2x_tx_kmem.v file
4.3.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) x
4.3.3.2.1. Intel KEYENC 4.3.3.2.2. Key Programmer
4.3.5. View the Results x
4.3.5.1. Push Buttons and LED Functions
4.6. Debug Guidelines x
4.6.1. HDCP Status Signals 4.6.2. Modifying HDCP Software Parameters 4.6.3. Frequently Asked Questions (FAQ)
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. HDMI 2.0 Design Example (Support FRL = 0)
4. HDCP Over HDMI 2.0/2.1 Design Example
5. HDMI Intel® Arria® 10 FPGA IP Design Example User Guide Archives
6. Revision History for HDMI Intel® Arria® 10 FPGA IP Design Example User Guide

2.9. Clocking Scheme

The clocking scheme illustrates the clock domains in the HDMI Intel® FPGA IP design example.
Figure 18. HDMI 2.1 Design Example Clocking Scheme
Table 15.  Clocking Scheme Signals
Clock Signal Name in Design Description
Management Clock

mgmt_clk

A free running 100 MHz clock for these components:
  • Avalon-MM interfaces for reconfiguration
    • The frequency range requirement is between 100–125 MHz.
  • PHY reset controller for transceiver reset sequence
    • The frequency range requirement is between 1–500 MHz.
  • IOPLL Reconfiguration
    • The maximum clock frequency is 100 MHz.
  • RX Reconfiguration Management
  • TX Reconfiguration Management
  • CPU
  • I2C Master
I2C Clock i2c_clk

A 100 MHz clock input that clocks I2C slave, output buffers, SCDC registers, and link training process in the HDMI RX core, and EDID RAM.

TX PLL Reference Clock 0 tx_tmds_clk

Reference clock 0 to the TX PLL. The clock frequency is the same as the expected TMDS clock frequency from the HDMI TX TMDS clock channel. This reference clock is used in TMDS mode.

For this HDMI design example, this clock is connected to the RX TMDS clock for demonstration purpose. In your application, you need to supply a dedicated clock with TMDS clock frequency from a programmable oscillator for better jitter performance.

Note: Do not use a transceiver RX pin as a TX PLL reference clock. Your design will fail to fit if you place the HDMI TX refclk on an RX pin.
TX PLL Reference Clock 1 txfpll_refclk1/rxphy_cdr_refclk1

Reference clock to the TX PLL and RX CDR, as well as IOPLL for vid_clk. The clock frequency is 100 MHz.

TX PLL Serial Clock tx_bonding_clocks

Serial fast clock generated by TX PLL. The clock frequency is set based on the data rate.

TX Transceiver Clock Out tx_clk

Clock out recovered from the transceiver, and the frequency varies depending on the data rate and symbols per clock.

TX transceiver clock out frequency = Transceiver data rate/Transceiver width

For this HDMI design example, the TX transceiver clock out from channel 0 clocks the TX transceiver core input (tx_coreclkin), link speed IOPLL (pll_hdmi) reference clock, and the video and FRL IOPLL (pll_vid_frl) reference clock.

Video Clock tx_vid_clk/rx_vid_clk

Video clock to TX and RX core. The clock runs at a fixed frequency of 225 MHz.

TX/RX FRL Clock tx_frl_clk/rx_frl_clk

FRL clock to for TX and RX core.
RX TMDS Clock rx_tmds_clk

TMDS clock channel from the HDMI RX connector and connects to an IOPLL to generate the reference clock for CDR reference clock 0. The core uses this clock when it is in TMDS mode.

RX CDR Reference Clock 0 rxphy_cdr_refclk0

Reference clock 0 to RX CDR. This clock is derived from the RX TMDS clock. The RX TMDS clock frequency ranges from 25 MHz to 340 MHz while the RX CDR minimum reference clock frequency is 50 MHz.

An IOPLL is used to generate a 5 clock frequency for the TMDS clock between 25 MHz to 50 MHz and generate the same clock frequency for the TMDS clock between 50 MHz - 340 MHz.

RX Transceiver Clock Out rx_clk

Clock out recovered from the transceiver, and the frequency varies depending on the data rate and transceiver width.

RX transceiver clock out frequency = Transceiver data rate/Transceiver width

For this HDMI design example, the RX transceiver clock out from channel 1 clocks the RX transceiver core input (rx_coreclkin) and FRL IOPLL (pll_frl) reference clock.

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