HDMI Intel® Arria 10 FPGA IP Design Example User Guide

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ID 683156
Date 11/12/2021
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices 2. HDMI 2.1 Design Example (Support FRL = 1) 3. HDMI 2.0 Design Example (Support FRL = 0) 4. HDCP Over HDMI 2.0/2.1 Design Example 5. HDMI Intel® Arria® 10 FPGA IP Design Example User Guide Archives 6. Revision History for HDMI Intel® Arria® 10 FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices x
1.1. Generating the Design 1.2. Simulating the Design 1.3. Compiling and Testing the Design 1.4. HDMI Intel® FPGA IP Design Example Parameters
2. HDMI 2.1 Design Example (Support FRL = 1) x
2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.2. Creating RX-Only or TX-Only Designs 2.3. Hardware and Software Requirements 2.4. Directory Structure 2.5. Design Components 2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 2.7. Design Software Flow 2.8. Running the Design in Different FRL Rates 2.9. Clocking Scheme 2.10. Interface Signals 2.11. Design RTL Parameters 2.12. Hardware Setup 2.13. Simulation Testbench 2.14. Design Limitations 2.15. Debugging Features 2.16. Upgrading Your Design
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.15. Debugging Features x
2.15.1. Software Debugging Message 2.15.2. SCDC Information from the Sink Connected to TX 2.15.3. Clock Frequency Measurement
3. HDMI 2.0 Design Example (Support FRL = 0) x
3.1. HDMI 2.0 RX-TX Retransmit Design Block Diagram 3.2. Hardware and Software Requirements 3.3. Directory Structure 3.4. Design Components 3.5. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 3.6. Clocking Scheme 3.7. Interface Signals 3.8. Design RTL Parameters 3.9. Hardware Setup 3.10. Simulation Testbench 3.11. Upgrading Your Design
4. HDCP Over HDMI 2.0/2.1 Design Example x
4.1. High-bandwidth Digital Content Protection (HDCP) 4.2. Nios II Processor Software Flow 4.3. Design Walkthrough 4.4. Protection of Encryption Key Embedded in FPGA Design 4.5. Security Considerations 4.6. Debug Guidelines
4.1. High-bandwidth Digital Content Protection (HDCP) x
4.1.1. HDCP Over HDMI Design Example Architecture
4.3. Design Walkthrough x
4.3.1. Set Up the Hardware 4.3.2. Generate the Design 4.3.3. Include HDCP Production Keys 4.3.4. Compile the Design 4.3.5. View the Results
4.3.3. Include HDCP Production Keys x
4.3.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) 4.3.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
4.3.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) x
4.3.3.1.1. HDCP Key Mapping from DCP Key Files 4.3.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 4.3.3.1.3. hdcp2x_rx_kmem.v file 4.3.3.1.4. hdcp2x_tx_kmem.v file
4.3.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) x
4.3.3.2.1. Intel KEYENC 4.3.3.2.2. Key Programmer
4.3.5. View the Results x
4.3.5.1. Push Buttons and LED Functions
4.6. Debug Guidelines x
4.6.1. HDCP Status Signals 4.6.2. Modifying HDCP Software Parameters 4.6.3. Frequently Asked Questions (FAQ)
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. HDMI 2.0 Design Example (Support FRL = 0)
4. HDCP Over HDMI 2.0/2.1 Design Example
5. HDMI Intel® Arria® 10 FPGA IP Design Example User Guide Archives
6. Revision History for HDMI Intel® Arria® 10 FPGA IP Design Example User Guide

6. Revision History for HDMI Intel® Arria® 10 FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2021.11.12 21.3 19.6.1
  • Updated the subsection Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) to describe the new key encryption software utility (KEYENC).
  • Removed the following figures:
    • Data array of Facsimile Key R1 for RX Private Key
    • Data arrays of HDCP Production Keys (Placeholder)
    • Data array of HDCP Protection Key (Predefined key)
    • HDCP protection key initialized in hdcp2x_tx_kmem.mif
    • HDCP protection key initialized in hdcp1x_rx_kmem.mif
    • HDCP protection key initialized in hdcp1x_tx_kmem.mif
  • Moved subsection HDCP Key Mapping from DCP Key Files from Debug Guidelines to Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0).
2021.09.15 21.1 19.6.0 Removed reference to ncsim
2021.05.12 21.1 19.6.0
  • Added When SUPPORT FRL = 1 or SUPPORT HDCP KEY MANAGEMENT = 1 to the description for Figure 29 HDCP Over HDMI Design Example Block Diagram.
  • Added the steps in HDCP key memory files in Design Walkthrough.
  • Added When SUPPORT FRL = 0 to the section Setup the Hardware.
  • Added the step to turn on Support HDCP Key Management parameter in Generate the Design.
  • Added a new subsection Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1).
  • Renamed Table Push Button and LED Indicators to Push Button and LED Indicators (SUPPORT FRL = 0).
  • Added Table Push Button and LED Indicators (SUPPORT FRL = 1).
  • Added a new chapter Protection of Encryption Key Embedded in FPGA Design.
  • Added a new chapter Debug Guidelines and subsections HDCP Status Signals, Modifying HDCP Software Parameter and Frequently Asked Questions.
2021.04.01 21.1 19.6.0
  • Updated Figure Components Required for RX-Only or TX-Only Design.
  • Updated Table Generated RTL Files.
  • Updated Figure HDMI RX Top Components.
  • Removed Section HDMI RX Top Link Training Process.
  • Updated the steps in Running the Design in Different FRL Rates.
  • Updated Figure HDMI 2.1 Design Example Clocking Scheme.
  • Updated Table Clocking Scheme Signals.
  • Updated Figure HDMI RX-TX Block Diagram to add a connection from Transceiver Arbiter to TX top.
2020.09.28 20.3 19.5.0
  • Removed the note that the HDMI 2.1 design example in FRL mode supports only speed grade –1 devices in the HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices and HDMI 2.1 Design Example (Support FRL = 1) sections. The design supports all speed grades.
  • Removed ls_clk information from all HDMI 2.1 design example related sections. The ls_clk domain is no longer used in the design example.
  • Updated the block diagrams for the HDMI 2.1 design example in FRL mode in the HDMI 2.1 Design Example (Support FRL = 1), Creating RX-Only or TX-Only Designs Design Components, and Clocking Scheme sections.
  • Updated the directories and generated files list in the Directory Structure sections.
  • Removed irrelevant signals, and added or edited the description of the following HDMI 2.1 design example signals in the Interface Signals section:
    • sys_init
    • txpll_frl_locked
    • tx_os
    • txphy_rcfg* signals
    • tx_reconfig_done
    • txcore_tbcr
    • pio_in0_external_connection_export
  • Added the following parameters in the Design RTL Parameters section:
    • EDID_RAM_ADDR_WIDTH
    • BITEC_DAUGHTER_CARD_REV
    • USE FPLL
    • POLARITY_INVERSION
  • Updated the block diagrams for the HDMI 2.0 design example for Intel® Quartus® Prime Pro Edition software in the HDMI 2.0 Design Example (Support FRL = 0), Creating RX-Only or TX-Only Designs Design Components, and Clocking Scheme sections.
  • Updated the clock and reset signal names in the Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering section.
  • Removed irrelevant signals, and added or edited the description of the following HDMI 2.0 design example signals in the Interface Signals section:
    • clk_fpga_b3_p
    • REFCLK_FMCB_P
    • fmcb_la_tx_p_11
    • fmcb_la_rx_n_9e
    • fr_clck
    • reset_xcvr_powerup
    • nios_tx_i2c* signals
    • hdmi_ti_i2c* signals
    • tx_i2c_avalon* signals
    • clock_bridge_0_in_clk_clk
    • reset_bridge_0_reset_reset_n
    • i2c_master* signals
    • nios_tx_i2c* signals
    • measure_valid_pio_external_connection_export
    • oc_i2c_av_slave_translator_avalon_anti_slave_0* signals
    • powerup_cal_done_export
    • rx_pma_cal_busy_export
    • rx_pma_ch_export
    • rx_pma_rcfg_mgmt* signals
  • Added a note that the simulation testbench is not supported for designs with the Include I2C parameter enabled and updated the simulation message in the Simulation Testbench section.
  • Updated the Upgrading Your Design section.
2020.04.13 20.1 19.4.0
  • Added a note that the HDMI 2.1 design example in FRL mode supports only speed grade –1 devices in the HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices and Detailed Description for HDMI 2.1 Design Example (Support FRL = 1) sections.
  • Moved the HDCP Over HDMI Design Example for Intel® Arria® 10 Devices section from the HDMI Intel® FPGA IP User Guide.
  • Edited the Simulating the Design section to include the audio sample generator, sideband data generator, and auxiliary data generator and updated the successful simulation message.
  • Removed the note that stated simulation is available only for Support FRL disabled designs note. Simulation is now available for Support FRL enabled designs as well.
  • Updated the feature description in the Detailed Description for HDMI 2.1 Design Example (Support FRL Enabled) section.
  • Edited the block diagram in the HDMI 2.1 RX-TX Design Block Diagram, Design Components, and Creating RX-Only or TX-Only Designs sections for HDMI 2.1 design example. Added new components and removed components that are no longer applicable.
  • Edited the main.c script instruction in the Creating RX-Only or TX-Only Designs section.
  • Updated the Directory Structure sections to add new folders and files for both HDMI 2.0 and HDMI 2.1 design examples.
  • Updated the Hardware and Software Requirements section for HDMI 2.1 design example.
  • Updated the block diagram and the signal descriptions in the Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering section for HDMI 2.1 design example.
  • Added a new section, Running the Design in Different FRL Rates, for the HDMI 2.1 design examples.
  • Updated the block diagram and the signal descriptions in the Clocking Scheme section for HDMI 2.1 design example.
  • Added description about user DIP switch in the Hardware Setup section for HDMI 2.1 design example.
  • Updated the Design Limitations section for HDMI 2.1 design example.
  • Updated the Upgrading Your Design section.
  • Updated the Simulation Testbench sections for both HDMI 2.0 and HDMI 2.1 design examples.
2020.01.16 19.4 19.3.0
  • Updated the HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices section with information about the newly added HDMI 2.1 design example with FRL mode.
  • Added a new chapter, Detailed Description for HDMI 2.1 Design Example (Support FRL Enabled) that contains all the relevant information about the newly added design example.
  • Renamed the HDMI Intel FPGA IP Design Example Detailed Description to Detailed Description for HDMI 2.0 Design Example for better clarity.
2019.10.31 18.1 18.1
  • Added generated files in the tx_control_src folder: ti_i2c.c and ti_i2c.h.
  • Added support for FMC daughter card revision 11 in the Hardware and Software Requirements and Compiling and Testing the Design sections.
  • Removed the Design Limitation section. The limitation regarding the timing violation on the maximum skew constraints was resolved in version 18.1 of the HDMI Intel® FPGA IP.
  • Added a new RTL parameter, BITEC_DAUGHTER_CARD_REV, to enable you to select the revision of the Bitec HDMI daughter card.
  • Updated the description for fmcb_dp_m2c_p and fmcb_dp_c2m_p signals to include information about the FMC daughter card revisions 11, 6, and 4.
  • Added the following new signals for Bitec daughter card revision 11:
    • hdmi_tx_ti_i2c_sda
    • hdmi_tx_ti_i2c_scl
    • oc_i2c_master_ti_avalon_anti_slave_address
    • oc_i2c_master_ti_avalon_anti_slave_write
    • oc_i2c_master_ti_avalon_anti_slave_readdata
    • oc_i2c_master_ti_avalon_anti_slave_writedata
    • oc_i2c_master_ti_avalon_anti_slave_waitrequest
  • Added a section about Upgrading Your Design.
2017.11.06 17.1 17.1
  • Renamed HDMI IP core to HDMI Intel® FPGA IP as per Intel rebranding.
  • Changed the term Qsys to Platform Designer.
  • Added information about Dynamic Range and Mastering InfoFrame (HDR) insertion and filtering feature.
  • Updated the directory structure:
    • Added script and software folders and files.
    • Updated common and hdr files.
    • Removed atx files.
    • Differentiated files for Intel® Quartus® Prime Standard Edition and Intel® Quartus® Prime Pro Edition.
  • Updated the Generating the Design section to add the device used as 10AX115S2F4I1SG.
  • Edited the transceiver data rate for 50-100 MHz TMDS clock frequency to 2550-5000 Mbps.
  • Updated the RX-TX link information that you can release the user_pb[2] button to disable external filtering.
  • Updated the Nios II software flow diagram that involves the controls for I2C master and HDMI source.
  • Added information about the Design Example GUI parameters.
  • Added HDMI RX and TX Top design parameters.
  • Added these HDMI RX and TX top-level signals:
    • mgmt_clk
    • reset
    • i2c_clk
    • hdmi_clk_in
    • Removed these HDMI RX and TX top-level signals:
      • version
      • i2c_clk
  • Added a note that the transceiver analog setting is tested for the Intel® Arria® 10 FPGA Development Kit and Bitec HDMI 2.0 Daughter card. You may modify the analog setting for your board.
  • Added a link for workaround to avoid jitter of PLL cascading or non-dedicated clock paths for Intel® Arria® 10 PLL reference clock.
  • Added a note that you cannot use a transceiver RX pin as a CDR refclk for HDMI RX or as a TX PLL refclk for HDMI TX.
  • Added a note about how to add set_max_skew constraint for designs that use TX PMA and PCS bonding.
2017.05.08 17.0 17.0
  • Rebranded as Intel.
  • Changed part number.
  • Updated the directory structure:
    • Added hdr files.
    • Changed qsys_vip_passthrough.qsys to nios.qsys.
    • Added files designated for Intel® Quartus® Prime Pro Edition.
  • Updated information that the RX-TX Link block also performs external filtering on the High Dynamic Range (HDR) Infoframe from the HDMI RX auxiliary data and inserts an example HDR Infoframe to the auxiliary data of the HDMI TX through Avalon ST multiplexer.
  • Added a note for the Transceiver Native PHY description that to meet the HDMI TX inter-channel skew requirement, you need to set the TX channel bonding mode option in the Arria 10 Transceiver Native PHY parameter editor to PMA and PCS bonding.
  • Updated description for os and measure signals.
  • Modified the oversampling factor for different transceiver data rate at each TMDS clock frequency range to support TX FPLL direct clock scheme.
  • Changed TX IOPLL to TX FPLL cascade clocking scheme to TX FPLL direct scheme.
  • Added TX PMA reconfiguration signals.
  • Edited USER_LED[7] oversampling status. 1 indicates oversampled (data rate < 1,000 Mbps in Arria 10 device).
  • Updated HDMI Design Example Supported Simulators table. VHDL not supported for NCSim.
  • Added link to archived version of the Arria 10 HDMI IP Core Design Example User Guide.
2016.10.31 16.1 16.1 Initial release.
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