Visible to Intel only — GUID: pjz1575017665418
Ixiasoft
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Arria® 10 Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. HDMI 2.0 Design Example (Support FRL = 0)
4. HDCP Over HDMI 2.0/2.1 Design Example
5. HDMI Intel® Arria® 10 FPGA IP Design Example User Guide Archives
6. Revision History for HDMI Intel® Arria® 10 FPGA IP Design Example User Guide
2.1. HDMI 2.1 RX-TX Retransmit Design Block Diagram
2.2. Creating RX-Only or TX-Only Designs
2.3. Hardware and Software Requirements
2.4. Directory Structure
2.5. Design Components
2.6. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
2.7. Design Software Flow
2.8. Running the Design in Different FRL Rates
2.9. Clocking Scheme
2.10. Interface Signals
2.11. Design RTL Parameters
2.12. Hardware Setup
2.13. Simulation Testbench
2.14. Design Limitations
2.15. Debugging Features
2.16. Upgrading Your Design
3.1. HDMI 2.0 RX-TX Retransmit Design Block Diagram
3.2. Hardware and Software Requirements
3.3. Directory Structure
3.4. Design Components
3.5. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering
3.6. Clocking Scheme
3.7. Interface Signals
3.8. Design RTL Parameters
3.9. Hardware Setup
3.10. Simulation Testbench
3.11. Upgrading Your Design
Visible to Intel only — GUID: pjz1575017665418
Ixiasoft
2.12. Hardware Setup
The HDMI FRL-enabled design example is HDMI 2.1 capable and performs a loop-through demonstration for a standard HDMI video stream.
To run the hardware test, connect an HDMI-enabled device—such as a graphics card with HDMI interface—to the HDMI sink input. The design supports both HDMI 2.1 or HDMI 2.0/1.4b source and sink.
- The HDMI sink decodes the port into a standard video stream and sends it to the clock recovery core.
- The HDMI RX core decodes the video, auxiliary, and audio data to be looped back in parallel to the HDMI TX core through the DCFIFO.
- The HDMI source port of the FMC daughter card transmits the image to a monitor.
Note: If you want to use another Intel FPGA development board, you must change the device assignments and the pin assignments. The transceiver analog setting is tested for the Intel® Arria® 10 FPGA development kit and Bitec HDMI 2.1 daughter card. You may modify the settings for your own board.
Push Button/LED | Function |
---|---|
cpu_resetn | Press once to perform system reset. |
user_dipsw | User-defined DIP switch to toggle the passthrough mode.
Refer to Running the Design in Different FRL Rates for more information about setting the different FRL rates. |
user_pb[0] | Press once to toggle the HPD signal to the standard HDMI source. |
user_pb[1] | Reserved. |
user_pb[2] |
Press once to read the SCDC registers from the sink connected to the TX of the Bitec HDMI 2.1 FMC daughter card.
Note: To enable read, you must set DEBUG_MODE to 1 in the software.
|
USER_LED[0] |
RX TMDS clock PLL lock status.
|
USER_LED[1] |
RX transceiver ready status.
|
USER_LED[2] |
RX link speed clock PLL, and RX video and FRL clock PLL lock status.
|
USER_LED[3] |
RX HDMI core alignment and deskew lock status.
|
USER_LED[4] |
RX HDMI video lock status.
|
USER_LED[5] |
TX link speed clock PLL, and TX video and FRL clock PLL lock status.
|
USER_LED[6] |
TX transceiver ready status.
|
USER_LED[7] |
TX link training status.
|