OCT Intel® FPGA IP User Guide

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ID 683708
Date 7/03/2019
Public
Document Table of Contents
Document Table of Contents x
OCT Intel® FPGA IP User Guide
OCT Intel® FPGA IP User Guide x
OCT Intel® FPGA IP Features OCT Intel® FPGA IP Overview OCT Intel® FPGA IP Functional Description OCT Intel® FPGA IP Design Example OCT Intel® FPGA IP References OCT Intel® FPGA IP User Guide Archives Document Revision History for OCT Intel® FPGA IP User Guide
OCT Intel® FPGA IP Overview x
RZQ Pin OCT Block OCT Logic
OCT Intel® FPGA IP Functional Description x
Power-Up Mode Interfaces User Mode OCT
User Mode OCT x
Core FSM
OCT Intel® FPGA IP Design Example x
Generating the Intel® Quartus® Prime Design Example
OCT Intel® FPGA IP References x
OCT Intel® FPGA IP Parameter Settings OCT Intel® FPGA IP Signals QSF Assignments IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices x
Migrating Your ALTOCT IP to the OCT Intel® FPGA IP
OCT Intel® FPGA IP User Guide

OCT Intel® FPGA IP User Guide

Updated for:
Intel® Quartus® Prime Design Suite 19.2
IP Version 19.1

The OCT Intel® FPGA IP allows you to dynamically calibrate I/O with reference to an external resistor. The OCT IP improves signal integrity, reduces board space, and is necessary for communicating with external devices such as memory interfaces.

The OCT IP is available for Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices. If you are migrating designs from Stratix® V, Arria® V, and Cyclone® V devices, you need to migrate the IP. For more details, refer to the related information.

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