Ethernet Support Center

The Ethernet IP Support Center provides information on how to select, design, and implement Ethernet links. There are also guidelines on how to bring up your system and debug the Ethernet links. This page is organized into categories that align with an Ethernet system design flow from start to finish.

Get support resources for Intel Agilex® 7, Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 devices from the pages below. For other devices, search from the following links: FPGA Documentation Index, Training Courses, Quick Videos, Design Examples, and Knowledge Base.

Getting Started

Intel Agilex® 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines

Intel Agilex 7 Device Schematic Review Worksheet

1. Device and IP Selection

Which Intel® FPGA Family Should I Use?

Refer to Table 1 to understand the Ethernet intellectual property (IP) core support for Intel Agilex, Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 devices. Compare between the four devices to select the right device for your Ethernet subsystem implementation.

Please refer to the respective user guides to understand and find out whether the various features listed in the table above are mutually exclusive. For example: Intel FPGA IP for Low Latency 100 Gbps Ethernet (for Intel Arria 10 devices) does not allow you to enable the RS-FEC and 1588 PTP simultaneously.

2. Design Flow and IP Integration

Where Can I Find Information on IP Integration?

Refer to the Getting Started section of your chosen IP core user guide. You can also refer to the following documents for details:

Intel Arria 10 Devices

• AN 735: Intel® FPGA Low Latency Ethernet 10G MAC IP Core Migration Guidelines
• AN 795: Implementing Guidelines for 10G Ethernet Subsystem Using Low Latency 10G MAC IP Core in Arria® 10 Devices
• AN 808: Migrating Guidelines from Intel Arria® 10 to Intel Stratix® 10 for 10G Ethernet Subsystem

Intel Stratix 10 Devices

• AN 778: Intel Stratix 10 Transceiver Usage

Intel Agilex Devices

• Intel Agilex® 7 F-Series and I-Series General-Purpose I/O User Guide
• Intel Agilex® 7 Configuration User Guide

Which Ethernet IP Core Should I Use?

Intel® FPGA IP for Ethernet

The Intel FPGA IP for Ethernet portfolio contains various IP types to support data rates from 10 Mbps to 100 Gbps. Ethernet IP solutions encompass the Media Access Controller and PHY IP core, which includes both the physical medium attachment (PMA) and physical coding sublayer (PCS). For more information, refer to the following user guides:

Intel Agilex Devices

• Intel® E-Tile Hard IP for Ethernet Intel FPGA IP User Guide
• Intel E-Tile Transceiver PHY User Guide
• Intel E-Tile Channel Placement Tool
• Intel Agilex® 7 Device Data Sheet

Intel Stratix 10 Devices

• Intel FPGA Triple Speed Ethernet IP Core User Guide
• Intel FPGA Low Latency Ethernet 10G MAC IP Core User Guide
• Intel Stratix 10 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core User Guide
• Intel Stratix 10 10GBASE-KR PHY IP Core User Guide
• Intel Stratix 10 Low Latency 40-Gbps Ethernet IP Core User Guide
• Intel Stratix 10 Low Latency 100-Gbps Ethernet IP Core User Guide
• Intel Stratix 10 E-Tile Hard IP for Ethernet Intel FPGA IP User Guide
• Intel Stratix 10 E-Tile Transceiver PHY User Guide
• Intel Stratix 10 H-Tile Hard IP for Ethernet Intel FPGA IP User Guide
• Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide
• Intel Stratix 10 Device Datasheet
• Intel E-Tile Channel Placement Tool

Intel Arria 10 Devices

• Intel FPGA Triple Speed Ethernet IP Core User Guide
• Intel FPGA Low Latency Ethernet 10G MAC IP Core User Guide
• 25 Gbps Ethernet IP Core User Guide
• 50 Gbps Ethernet IP Core User Guide
• Low Latency 40 Gbps Ethernet IP Core User Guide
• Low Latency 100 Gbps Ethernet IP Core User Guide
• Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

Intel Cyclone 10 Devices

• Intel FPGA Triple Speed Ethernet IP Core User Guide
• Intel FPGA Low Latency Ethernet 10G MAC IP Core User Guide

3. Board Design and Power Management

Pin Connection Guidelines

Intel Cyclone 10 Devices

• Intel Cyclone 10 GX Device Family Pin Connection Guidelines

Intel Arria 10 Devices

• Intel Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines

Intel Stratix 10 Devices

• Intel Stratix 10 GX, MX, TX, DX, and SX Device Family Pin Connection Guidelines

Intel Agilex Devices

• Intel Agilex® 7 Device Family Pin Connection Guidelines

Schematic Review

Intel Cyclone 10 Devices

• Intel Cyclone 10 GX Schematic Review Worksheet

Intel Arria 10 Devices

• Intel Arria 10 GX, GT, and SX Schematic Review Worksheet

Intel Stratix 10 Devices

• Intel Stratix 10 GX, MX, TX and SX Schematic Review Worksheet

Intel Agilex Devices

• Intel Agilex Device Schematic Review Worksheet

Board Design Guidelines

• Board Layout Test
• AN 114: Board Design Guidelines for Intel® Programmable Device Packages
  
• AN 766: Intel Stratix 10 Devices, High-Speed Signal Interface Layout Design Guideline
• AN 613: PCB Stackup Design Considerations for Intel FPGAs
• AN 875: Intel Stratix 10 E-Tile PCB Design Guidelines
• AN 886: Intel Agilex® 7 Device Design Guidelines
• Intel Agilex® 7 Power Management User Guide
• Intel Agilex® 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines
• AN 910: Intel Agilex® 7 Power Distribution Network Design Guidelines

Early Power Estimator

• Early Power Estimator (EPE) and Power Analyzer
• AN 750: Using the Intel FPGA PDN Tool to Optimize Your Power Delivery Network Design
• Device-Specific Power Deliver Network (PDN) Tool 2.0 User Guide

Thermal Power Guidelines

• AN 787: Intel Stratix 10 Thermal Modeling and Management

Power Sequencing Guidelines

• AN 692: Power Sequencing Considerations for Intel® Cyclone® 10 GX, Intel® Arria® 10, Intel® Stratix® 10, and Intel Agilex® 7 Devices

4. Design Examples and Reference Designs

Intel Arria 10 Devices

• Triple-Speed Ethernet
• AN647: Single-Port Triple Speed Ethernet and On-Board PHY Chip Reference Design
• AN-744: Scalable Triple Speed Ethernet Reference Design for Intel Arria 10 Devices
• Intel Arria 10 Triple Speed Ethernet and Native PHY Design Example
• Intel Arria 10 Triple Speed Ethernet with IEEE 1588v2 and Native PHY Design Example
• 10G Ethernet
• AN 699: Using the Intel® FPGA Ethernet Design Toolkit
• AN794: Intel Arria 10 Low Latency Ethernet 10G MAC and XAUI PHY Reference Design
• AN 701: Scalable Low Latency Ethernet 10G MAC using Intel Arria 10 1G/10G PHY
• AN 838: Interoperability between Intel Arria 10 NBASE-T Ethernet Solution with Aquantia Ethernet PHY Reference Design
• Intel Arria 10 SoC Scalable Multi-speed 10M-10G Ethernet Design Example
• Intel Arria 10 Scalable 10G Ethernet MAC + Native PHY with IEEE 1588v2 Design Example

Intel Stratix 10 Devices

• Triple-Speed Ethernet
• AN830: Intel FPGA Triple Speed Ethernet and On Board PHY Chip Reference Design
• 1G/2.5G Ethernet
• 1G/2.5G Ethernet Design Example for Intel Stratix 10
• 10G Ethernet
• Intel FPGA IP for Low Latency Ethernet 10G MAC design example user guide
• 40G Ethernet
• Intel FPGA IP for Low Latency 40-Gbps Ethernet design example user guide
• Intel FPGA H-Tile Hard IP for Ethernet
• Design example user guide
• 100G Ethernet
• Intel FPGA IP for Low Latency 100-Gbps Ethernet design example user guide
• E-Tile Hard IP for Ethernet Intel Stratix 10
• FPGA IP Design Example User Guide

Intel Agilex 7 Devices

• E-Tile Hard IP for Ethernet Intel Agilex Devices
  • FPGA IP Design Example User Guide
• Triple-Speed Ethernet IP
• F-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide
• 10G Ethernet IP
  • F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
• 25G Ethernet IP
  • F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide
• F-Tile Ethernet Hard IP
  • F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide
  • F-Tile Dynamic Reconfiguration Design Example User Guide

Additional Resources

• Timing closure Guidelines
• Partial Reconfiguration
• Remote System Update
• Remote System Debug
• Intel FPGA Wiki

5. Debug

Tools

Intel Stratix 10 Device Ethernet Link Inspector

Ethernet Link Inspector consists of two sub-tools:

1. Link Monitor - Allows you to continuously monitor health of Ethernet link(s) between Intel Stratix 10 device and the link partner. Some of the key features you can monitor are: Link status summary (CDR lock, RX recovered frequency, lane alignment lock etc..) MAC packet statistics, FEC statistics etc.
2.  Link Analysis - Allows you to have transparency into the link bring up sequence (like Auto-negotiation, Link Training etc.) or any other event captured in the Signal Tap Logic Analyzer file. Configure & capture the Signal Tap Logic Analyzer file for given event and then use Link Analysis to import the captured event & study Intel Stratix 10 behavior during that event duration.
   

To access Ethernet Link Inspector for a specific Intel® Quartus® software version, please refer to the table below.

• For IP and Device support use model, refer to section ‘1.2 Supported IP Cores and Devices’ in the relevant Ethernet Link Inspector user guide.

Intellectual Property (IP) Core Release Notes

Intel Cyclone 10 Devices

• Intel FPGA Triple Speed Ethernet IP Core Release Notes
• Intel FPGA Low Latency Ethernet 10G MAC IP Core Release Notes

Intel Arria 10 Devices

• Intel FPGA Triple Speed Ethernet IP Core Release Notes
• Intel FPGA Low Latency Ethernet 10G MAC IP Core Release Notes
• 1G/10G and Backplane Ethernet 10GBASE-KR PHY Release Notes
• 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core Release Notes
• 25G Ethernet IP Core Release Notes
• Low Latency 40Gbps Ethernet IP Core Release Notes
• Low Latency 100-Gbps Ethernet IP Core Release Notes

Intel Stratix 10 Devices

• Intel FPGA Triple Speed Ethernet IP Core Release Notes
• Intel FPGA Low Latency Ethernet 10G MAC IP Core Release Notes
• Intel Stratix 10 10GBASE-KR PHY Release Notes
• Intel Stratix 10 H-Tile Hard IP for Ethernet IP Core Release Notes
• Intel Stratix 10 Low Latency 40-Gbps Ethernet IP Core Release Notes
• Intel Stratix 10 Low Latency 100-Gbps Ethernet IP Core Release Notes
• Intel Stratix 10 E-Tile Hard IP for Ethernet Intel FPGA IP Release Notes

Intel Agilex Devices

• E-Tile Hard IP for Ethernet Release Notes

Fault Tree Analysis Guides

• Fault Tree Analysis Guide for Low Latency 10G MAC Data Corruption Issue

Knowledge Base Solutions

Intel Cyclone 10 Devices

• Search the Knowledge Base (Intel FPGA IP for Triple Speed Ethernet)
• Search the Knowledge Base (Intel FPGA IP for Low Latency Ethernet 10G MAC)

Intel Arria 10 Devices

• Search the Knowledge Base (Intel FPGA IP for Triple-Speed Ethernet)
• Search the Knowledge Base (Intel FPGA IP for Low Latency Ethernet 10G MAC)
• Search the Knowledge Base (Intel FPGA IP for 1G/10G and Backplane Ethernet 10GBASE-KR PHY)
• Search the Knowledge Base (Intel FPGA IP for 1G/2.5G/5G/10G Ethernet Multi-rate PHY)
• Search the Knowledge Base (Intel FPGA IP for 25G Ethernet)
• Search the Knowledge Base (Intel FPGA IP for Low Latency 40 Gbps Ethernet)
• Search the Knowledge Base (Intel FPGA IP for Low Latency 100 Gbps Ethernet)

Intel Stratix 10 Devices

• Search the Knowledge Base (Intel FPGA IP for Triple Speed Ethernet)
• Search the Knowledge Base (Intel FPGA IP for Low Latency Ethernet 10G MAC)
• Search the Knowledge Base (Intel FPGA IP for 1G/2.5G/5G/10G Ethernet Multi-rate PHY)
• Search the Knowledge Base (Intel FPGA IP for 25G Ethernet)
• Search the Knowledge Base (Intel FPGA IP for Low Latency 40 Gbps Ethernet)
• Search the Knowledge Base (Intel FPGA IP for Low Latency 100 Gbps Ethernet)

Intel Agilex Devices

• Search the Knowledge Base (Intel FPGA IP for Intel Agilex® FPGAs and SoC FPGAs)

Intel® FPGA Technical Training

• Technical Training Catalog

6. Training Courses and Videos