The advantages of a differential clock over a single-ended clock scheme are:
For the single-ended clock input option, SSN can impact the clock input, even if the clock frequency is low frequency below 100 MHz. As shown in Figure 1, when the multi-aggressor input or output signals toggle simultaneously in one bank, large SSN is induced, that degrades power and ground integrity. When the input clock it is degraded by SSN, it can cause the PLL to lose lock, and cause the counter to malfunction. To limit SSN and crosstalk, you must restrict the number of switching outputs in a single bank. If the single-ended clock input is close to the potential crosstalk aggressor signal, it may also result in crosstalk that can cause a glitch in the victim single-ended clock signal.
Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III devices are designed with wire-bond packages. The inductive coupling between adjacent pins of a wire-bonded package can result in a higher noise. The package inductance of a two-layer wire-bond package is much higher compared to that of a 4-layer package, because it does not have a good reference plane.