Intel® Cyclone® 10 GX Device Design Guidelines

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ID 683703
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 GX Device Design Guidelines
Intel® Cyclone® 10 GX Device Design Guidelines x
System Specification Device Selection Early System and Board Planning Pin Connection Considerations for Board Design I/O and Clock Planning Design Entry Design Implementation, Analysis, Optimization, and Verification Design Checklist Appendix: Cyclone® 10 GX Transceiver Design Guidelines Conclusion Document Revision History
System Specification x
Design Specifications IP Selection Platform Designer
Device Selection x
Logic, Memory, and Multiplier Density I/O Pin Count, LVDS Channels, and Package Offering PLLs and Clock Routing Speed Grade Vertical Device Migration
Early System and Board Planning x
Early Power Estimation Temperature Sensing for Thermal Management Voltage Sensor Planning for Device Configuration Planning for On-Chip Debugging
Planning for Device Configuration x
Configuration Scheme Selection Configuration Features Quartus Prime Configuration Settings
Configuration Scheme Selection x
Serial Configuration Devices Download Cables Using the Parallel Flash Loader Intel® FPGA IP with MAX Devices
Configuration Features x
Data Compression Design Security Using Configuration Bitstream Encryption Remote System Upgrades SEU Mitigation and CRC Error Checks
Planning for On-Chip Debugging x
On-Chip Debugging Tools Planning Guidelines for Debugging Tools
Pin Connection Considerations for Board Design x
Device Power-Up Power Pin Connections and Power Supplies Configuration Pin Connections Board-Related Quartus Prime Settings Signal Integrity Considerations Board-Level Simulation and Advanced I/O Timing Analysis
Power Pin Connections and Power Supplies x
Decoupling Capacitors PLL and Transceiver Board Design Guidelines
Configuration Pin Connections x
DCLK and TCK Signal Integrity JTAG Pins MSEL Configuration Mode Pins Other Configuration Pins
Board-Related Quartus Prime Settings x
Device-Wide Output Enable Pin Unused Pins
Signal Integrity Considerations x
High-Speed Board Design Voltage Reference Pins Simultaneous Switching Noise I/O Termination
I/O and Clock Planning x
Making FPGA Pin Assignments Early Pin Planning and I/O Assignment Analysis I/O Features and Pin Connections Clock and PLL Selection PLL Feature Guidelines Clock Control Block I/O Simultaneous Switching Noise
I/O Features and Pin Connections x
I/O Signaling Type Selectable I/O Standards and Flexible I/O Banks Memory Interfaces Dual-Purpose and Special Pin Connections Cyclone® 10 GX I/O Features
PLL Feature Guidelines x
Clock Feedback Mode Clock Outputs
Design Entry x
Design Recommendations Using IP Cores Reconfiguration Recommended HDL Coding Styles Register Power-Up Levels and Control Signals Planning for Hierarchical and Team-Based Design
Reconfiguration x
Dynamic Reconfiguration
Planning for Hierarchical and Team-Based Design x
Planning Design Partitions Planning in Bottom-Up and Team-Based Flows Creating a Design Floorplan
Design Implementation, Analysis, Optimization, and Verification x
Selecting a Synthesis Tool Device Resource Utilization Reports Quartus Prime Messages Timing Constraints and Analysis Area and Timing Optimization Preserving Performance and Reducing Compilation Time Simulation Formal Verification Power Analysis Power Optimization
Timing Constraints and Analysis x
Recommended Timing Optimization and Analysis Assignments
Power Optimization x
Device and Design Power Optimization Techniques Quartus Prime Power Optimization Techniques
Device and Design Power Optimization Techniques x
Clock Power Management Memory Power Reduction I/O Power Guidelines
Quartus Prime Power Optimization Techniques x
Power Optimization Advisor
Appendix: Cyclone® 10 GX Transceiver Design Guidelines x
Transceiver PHY Architecture Overview Transceiver Bank Architecture PHY Layer Transceiver Components Transceiver Phase-Locked Loops Clock Generation Block (CGB) Calibration Transceiver Design Flow
PHY Layer Transceiver Components x
The GX Transceiver Channel
Transceiver Phase-Locked Loops x
Advanced Transmit (ATX) PLL Fractional PLL (fPLL) Channel PLL (CMU/CDR PLL)
Intel® Cyclone® 10 GX Device Design Guidelines

Intel® Cyclone® 10 GX Device Design Guidelines

Updated for:
Intel® Quartus® Prime Design Suite 17.1
This document provides a set of design guidelines, recommendations, and a list of factors to consider for designs that use Intel® FPGA (formerly Altera FPGA) Cyclone® 10 GX devices. This document also assists you with planning the FPGA and system early in the design process, which is crucial to successfully meet design requirements. For more information to help verify that you have followed each of the guidelines, use the “Design Checklist” topic in this app note.
Note: This application note does not include all Cyclone® 10 GX device details and features. For more information about Cyclone® 10 GX devices and features, refer to the " Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook".

The material references the Cyclone® 10 GX device architecture as well as aspects of the Intel® Quartus® Prime software and third-party tools that you might use in your design. The guidelines presented in this document can improve productivity and avoid common design pitfalls.

Table 1.  Summary of the Design Flow Stage and Guideline Topics
Stages of the Design Flow Guidelines
System Specification Planning design specifications, IP selection
Device Selection Device information, determining device variant and density, package offerings, migration, speed grade
Early System and Board Planning Early power estimation, thermal management option, planning for configuration scheme, planning for on-chip debugging
Pin Connection Considerations for Board Design Power-up, power pins, PLL connections, decoupling capacitors, configuration pins, signal integrity, board-level verification
I/O and Clock Planning Pin assignments, early pin planning, I/O features and connections, memory interfaces, clock and PLL selection, simultaneous switching noise (SSN)
Design Entry Coding styles and design recommendations, SOPC Builder, planning for hierarchical or team-based design
Design Implementation, Analysis, Optimization, and Verification Synthesis tool, device utilization, messages, timing constraints and analysis, area and timing optimization, compilation time, verification, power analysis and optimization
Figure 1.  Cyclone® 10 GX Device Design Flow

Section Content
System Specification
Device Selection
Early System and Board Planning
Pin Connection Considerations for Board Design
I/O and Clock Planning
Design Entry
Design Implementation, Analysis, Optimization, and Verification
Design Checklist
Appendix: Cyclone 10 GX Transceiver Design Guidelines
Conclusion
Document Revision History

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