PCI Express* IP Support Center

1. Device Selection

Intel® FPGA Device Family

Refer to the tables on page Intel® FPGA IP for PCIe* for Device Support for Number of Hardened PCI Express IP Blocks and Device Configurations and Features Support to understand the PCIe support for Intel FPGAs.

You can compare the devices in the tables and select the right device for your PCIe system implementation.

• Device Support and Number of Hardened PCIe IP Blocks Table
• Device Configurations and Features Support Table

2. User Guides and Reference Designs

The PCIe IP solutions encompass Intel’s technology-leading PCIe hardened protocol stack that includes the transaction and data link layers; and hardened physical layer, which includes both the physical medium attachment (PMA) and physical coding sublayer (PCS). Intel's PCIe IP also includes optional blocks, such as direct memory access (DMA) engines and single root I/O virtualization (SR-IOV). For more information, refer to the following user guides:

IP User Guides

Intel Agilex® 7 Devices

F-Tile IP User Guides

• Intel® FPGA F-Tile Avalon® Streaming IP for PCI Express User Guide
• AXI Streaming Intel® FPGA IP for PCI Express*

R-Tile IP User Guides

• Intel® FPGA R-Tile Avalon® Streaming IP for PCI Express User Guide
• AXI Streaming Intel® FPGA IP for PCI Express*

P-Tile IP User Guides

• Intel® FPGA P-Tile Avalon Streaming IP for PCI Express User Guide
  
• Intel® FPGA P-Tile Avalon Memory Mapped (Avalon-MM) IP for PCI Express User Guide
  
• Multi Channel DMA for PCI Express IP User Guide
• AXI Streaming Intel® FPGA IP for PCI Express*

Intel Stratix 10 Devices

P-Tile User Guides

• Intel® FPGA P-Tile Avalon-ST Hard IP for PCI Express User Guide
• Intel® FPGA P-Tile Avalon Memory Mapped IP for PCI Express User Guide
• Multi Channel DMA for PCI Express IP User Guide

H-Tile/L-Tile User Guides

• Multi Channel DMA for PCI Express IP User Guide
  
• Avalon Memory Mapped (Avalon-MM) Intel Stratix 10 Hard IP+ for PCI Express Solutions User Guide
• Intel® Stratix® 10 H-Tile/L-Tile Avalon Memory Mapped (AvalonMM) Hard IP for PCI Express User Guide
• Intel® Stratix® 10 Avalon Streaming (Avalon-ST) and Single Root I/O Virtualization (SR-IOV) Interface for PCI Express Solutions User Guide
• Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide

Intel Arria 10 and Intel Cyclone 10 Devices

• Intel® Arria® 10 and Intel Cyclone 10 GX Avalon Memory Mapped (Avalon-MM) Interface for PCI Express User Guide
  
• Intel® Arria® 10 or Intel Cyclone 10 GX Avalon Memory Mapped (Avalon-MM) DMA Interface for PCI Express Solutions User Guide
• Intel® Arria® 10 and Intel Cyclone 10 GX Avalon-ST Interface for PCI Express User Guide
• Intel® Arria® 10 Avalon Streaming (Avalon-ST) Interface with SR-IOV PCIe Solutions User Guide
• Intel® Quartus® Prime Pro Edition User Guide Partial Reconfiguration
• Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express User Guide

Design Example User Guides

Intel Agilex® 7 Devices

F-Tile Design Example User Guides

• Intel® FPGA F-Tile Avalon Streaming (Avalon-ST) IP for PCI Express Design Example User Guide

R-Tile Design Example User Guides

• Intel® FPGA R-Tile Avalon Streaming (Avalon-ST) IP for PCI Express Design Example User Guide
  

P-Tile Design Example User Guides

• Intel® FPGA P-Tile Avalon Streaming (Avalon-ST) IP for PCI Express Design Example User Guide
  
• Intel® FPGA P-Tile Avalon Memory Mapped (Avalon-MM) IP for PCI Express Design Example
• Multi Channel DMA for PCI Express IP Design Example User Guide

Intel Stratix 10 Devices

P-Tile Design Example User Guides

• Intel® FPGA P-Tile Avalon Streaming (Avalon-ST) IP for PCI Express Design Example User Guide
  
• Intel® FPGA P-Tile Avalon Memory Mapped (Avalon-MM) IP for PCI Express Design Example
• Multi Channel DMA for PCI Express IP Design Example User Guide

L/H-Tile Design Example User Guides

• Multi Channel DMA for PCI Express IP Design Example User Guide
  
• Intel® Stratix® 10 Avalon Streaming (Avalon-ST) IP for PCIe Design Example User Guide
• Intel® Stratix® 10 Avalon -MM Hard IP for PCIe Design Example User Guide

Intel Arria 10 and Intel Cyclone 10 Devices

• Intel® Arria® 10 and Intel Cyclone 10 Avalon-ST Hard IP for PCIe Design Example User Guide
• Intel® Arria® 10 and Intel Cyclone 10 Avalon-MM Interface for PCIe Design Example User Guide

IP Release Notes

Intel Agilex® 7 Devices

• P-Tile IP for PCI Express IP Core Release Notes
  
• Multi Channel DMA for PCI Express IP Release Notes

Intel Stratix 10 Devices

• L/H-Tile Hard IP for PCI Express IP Core Release Notes
  
• P-Tile IP for PCI Express IP Core Release Notes
• Multi Channel DMA for PCI Express IP Release Notes

Intel Arria 10 and Intel Cyclone 10 Devices

• Intel® Arria® 10 and Intel Cyclone 10 Hard IP for PCI Express IP Core Release Notes
  

PHY Interface for PCI Express (PIPE) Using the Intel Transceiver Native PHY IP Core

You can also implement just the physical layer of PCIe using the Transceiver Native PHY IP core and stitch it together with the remaining protocol layers implemented as soft logic in the FPGA fabric. This soft logic can be your own design or a third-party IP.

Find out more about the Transceiver Native PHY IP core in the PIPE chapter of the following user guides:

Intel Stratix 10 Devices

• L-Tile/H-Tile Transceiver PHY User Guide
  

Intel Arria 10 Devices

• Transceiver PHY User Guide
  

Intel Cyclone 10 Devices

• GX Transceiver PHY User Guide
  

Reference Designs

Intel Stratix 10 Devices

• Gen3x16 Avalon-MM DMA with Internal Memory Reference Design (AN 881)
  
• Gen3x16 Avalon-MM DMA with External Memory (DDR4) Reference Design (AN 881)
• Gen3x16 Avalon-MM DMA with HBM2 Reference Design (AN 881)
• Gen3x16 Using the Avery BFM for Simulation (AN 811)
• Gen3x8 Avalon-MM DMA with Internal Memory (Wiki)
• Gen3x8 Avalon -MM DMA with External DDR3/DDR4 Memory (AN 829)
• Gen3x8 Avalon-MM DMA for Legacy Quartus® Version (AN 690)
• Gen3x8 Partial Reconfiguration over PCI Express Reference Design (AN 819)

Intel Arria 10 Devices

• Gen3x8 Avalon-MM DMA with External DDR3 Memory (AN 708)
  
• Gen3x8 Avalon-MM DMA Reference Design with Internal Memory (AN 690)
• How to run Avalon-MM DMA Design Part1 (video)
• How to run Avalon-MM DMA Design Part2 (video)
• SoC Hardware Partial Reconfiguration
• Static Update Partial Reconfiguration Tutorial - Intel Arria 10 GX Device Only (AN 817)
• Hierarchical Partial Reconfiguration over PCIe (AN 813)
• Hierarchical Partial Reconfiguration Tutorial - Intel Arria 10 GX Device Only (AN 806)
• Partially Reconfiguring a Design - Intel Arria 10 GX Device Only (AN 797)
• Partial Reconfiguration over PCIe (AN 784)
• Upto Gen2x8 PCIe Root Port with MSI

Intel Cyclone 10 Devices

• Gen2x4 DMA Reference Design - Intel Cyclone 10 GX Device (AN 855)
  

Intel Legacy Devices

• DMA Reference Design for Legacy Devices (AN 456)

Development Kits

Stratix® V GX FPGA Development Kit

• PCIe AVMM with Direct Memory Access (DMA) and DDR3 Memory Interface
• AN708

Arria® V GT FPGA Development Kit

• PCIe AVMM with DMA and On-Chip Memory Interface
• Gen2x4 AVMM DMA - Arria V

Arria V GX Starter Kit

• PCIe AVMM with DMA and On-Chip Memory Interface

Cyclone® V GT FPGA Development Kit

• PCIe AVMM with DMA and On-Chip Memory Interface
• Gen2x4 AVMM DMA - Cyclone V
• PCIe AVMM with DMA and On-Chip Memory Interface (Linux Driver)
• Gen2x4 AVMM DMA - Arria V
• Gen2x4 AVMM DMA - Cyclone V

PCIe with On-chip Memory Interface Reference Designs
Stratix V GX FPGA Development Kit

• PCIe AVST and On-Chip Memory Interface
• AN456

Arria V GT FPGA Development Kit

• PCIe AVST and On-Chip Memory Interface

Cyclone V GT FPGA Development Kit

• PCIe AVST and On-Chip Memory Interface

Stratix IV GX FPGA Development Kit

• PCIe AVST and On-Chip Memory Interface

Cyclone IV GX FPGA Development Kit

• PCIe AVST and On-Chip Memory Interface

Arria II GX FPGA Development Kit

• PCIe AVST and On-Chip Memory Interface

Other PCIe Collateral Items and Tools

• Implementing MSI-X for PCI Express in Altera FPGA Devices

Stratix V GX FPGA Development Kit

• Transceiver Toolkit for hardened PCIe IP (Gen1x8)
• Transceiver Toolkit for hardened PCIe IP (Gen2x8)
• Transceiver Toolkit for hardened PCIe IP (Gen3x8)

Additional Resources

• Intel® Agilex® 7 SoC HPS Remote System Update
• Intel Arria 10 SoC Hardware Reference Design that Demonstrates Partial Reconfiguration
• Intel® Arria® 10 SoC Development Kit Remote System Debug
• Intel FPGA Wiki - Search Listings

3. IP Integration

Refer to the Getting Started section and Physical Layout of Hard IP section of your chosen IP core user guide. You can also refer to the following documents for details:

Intel Stratix 10 Devices

• How to Implement PCI Express (PIPE) in Intel Stratix 10 FPGA Transceivers section of the Intel Stratix L- and H-Tile Transceiver PHY User Guide
  
• AN 778: Intel Stratix 10 Transceiver Usage Application Note

Intel Arria 10 Devices

• How to Implement PCI Express (PIPE) in Intel Arria 10 FPGA Transceivers section of the Intel Arria 10 FPGA Transceiver PHY User Guide
  

Intel Cyclone 10 Devices

• How to Implement PCI Express (PIPE) in Intel Cyclone 10 GX FPGA Transceivers section of the Intel Cyclone 10 GX FPGA Transceiver PHY User Guide
  

4. Training Courses and Videos

Training Courses

• PCIe Training Courses

5. Debug

Intellectual Property (IP) Core Release Notes

Intel Agilex® 7 Devices

• P-Tile IP for PCI Express IP Core Release Notes
  
• Multi Channel DMA for PCI Express IP Release Notes

Intel Stratix 10 Devices

• Intel Stratix 10 Multi Channel DMA for PCI Express IP Release Notes
  
• L/H-Tile Hard IP for PCI Express IP Core Release Notes
• P-Tile IP for PCI Express IP Core Release Notes

Intel Arria 10 and Intel Cyclone 10 Devices

• Intel Arria 10 and Intel Cyclone 10 Hard IP for PCI Express IP Core Release Notes
  

Fault Tree Analysis Guides

• Fault Tree Analysis Guide for Intel Arria 10 Device PCI Express Solution

Knowledge Base Solution

• Search the Knowledge Base (Intel Agilex® Devices)
• Search the Knowledge Base (Intel® Stratix® 10 Devices)
  
• Search the Knowledge Base (Intel® Arria® 10 Devices)
• Search the Knowledge Base (Intel® Cyclone® 10 Devices)

FPGA Resource Placement Guidelines

• AN 778: Intel Stratix 10 Transceiver Usage Application Note

6. Additional Resources

Migrating to Intel Stratix 10 Devices

• Migrating to Intel Stratix 10 Devices from Intel Arria 10 Devices for the Avalon-MM and Avalon-MM DMA Interfaces AN 790
  
• Migrating to Intel Stratix 10 Devices for the Avalon Streaming Interface AN 791

PCIe-SIG Integrators List

• Intel FPGA products for the PCIe standard
• Intel non-programmable products for the PCIe standard