LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel®...

LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

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ID 683520

Date 9/20/2022

Version

Public

Document Table of Contents

Document Table of Contents x

LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices x

Release Information LVDS SERDES Intel® FPGA IP Features LVDS SERDES IP Core Functional Modes LVDS SERDES IP Core Functional Description LVDS SERDES IP Initialization and Reset LVDS SERDES Intel® FPGA IP Signals LVDS SERDES Intel® FPGA IP Parameter Settings LVDS SERDES Intel® FPGA IP Timing LVDS SERDES Intel® FPGA IP Design Examples Additional LVDS SERDES IP Core References LVDS SERDES Intel® FPGA IP User Guide Archives Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

LVDS SERDES IP Core Functional Description x

Serializer DPA FIFO Bitslip Deserializer

LVDS SERDES IP Initialization and Reset x

Initializing the LVDS SERDES IP in Non-DPA Mode Initializing the LVDS SERDES IP in DPA Mode Resetting the DPA Word Boundaries Alignment

Word Boundaries Alignment x

Aligning Word Boundaries

LVDS SERDES Intel® FPGA IP Parameter Settings x

LVDS SERDES Intel® FPGA IP General Settings LVDS SERDES Intel® FPGA IP PLL Settings LVDS SERDES Intel® FPGA IP Receiver Settings LVDS SERDES Intel® FPGA IP Transmitter Settings LVDS SERDES IP Core Clock Resource Summary

LVDS SERDES Intel® FPGA IP Receiver Settings x

Receiver Input Clock Parameters Setup

LVDS SERDES Intel® FPGA IP Transmitter Settings x

Setting the Transmitter Output Clock Parameters

LVDS SERDES Intel® FPGA IP Timing x

I/O Timing Analysis FPGA Timing Analysis Timing Analysis when Using PLL Core Clocks Timing Closure Guidelines for Internal FPGA Paths

I/O Timing Analysis x

Obtaining RSKM Report Obtaining TCCS Report

LVDS SERDES Intel® FPGA IP Design Examples x

LVDS SERDES IP Synthesizable Intel® Quartus® Prime Design Examples LVDS SERDES IP Simulation Design Example Combined LVDS SERDES IP Transmitter and Receiver Design Example LVDS SERDES IP Dynamic Phase Shift Design Example

Additional LVDS SERDES IP Core References x

IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices LVDS Interface with External PLL Mode LVDS Transmitters and Receivers in the Same I/O Bank Comparison of LVDS SERDES IP Core with Stratix® V SERDES

IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices x

Migrating Your ALTLVDS_TX and ALTLVDS_RX IP Cores

LVDS Interface with External PLL Mode x

IOPLL IP Signal Interface with LVDS SERDES IP IOPLL Parameter Values for External PLL Mode Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode

LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

Release Information

LVDS SERDES Intel® FPGA IP Features

LVDS SERDES IP Core Functional Modes

LVDS SERDES IP Core Functional Description

Serializer

DPA FIFO

Bitslip

Deserializer

LVDS SERDES IP Initialization and Reset

Initializing the LVDS SERDES IP in Non-DPA Mode

Initializing the LVDS SERDES IP in DPA Mode

Resetting the DPA

Word Boundaries Alignment

Aligning Word Boundaries

LVDS SERDES Intel® FPGA IP Signals

LVDS SERDES Intel® FPGA IP Parameter Settings

LVDS SERDES Intel® FPGA IP General Settings

LVDS SERDES Intel® FPGA IP PLL Settings

LVDS SERDES Intel® FPGA IP Receiver Settings

Receiver Input Clock Parameters Setup

LVDS SERDES Intel® FPGA IP Transmitter Settings

Setting the Transmitter Output Clock Parameters

LVDS SERDES IP Core Clock Resource Summary

LVDS SERDES Intel® FPGA IP Timing

I/O Timing Analysis

Obtaining RSKM Report

Obtaining TCCS Report

FPGA Timing Analysis

Timing Analysis when Using PLL Core Clocks

Timing Closure Guidelines for Internal FPGA Paths

LVDS SERDES Intel® FPGA IP Design Examples

LVDS SERDES IP Synthesizable Intel® Quartus® Prime Design Examples

LVDS SERDES IP Simulation Design Example

Combined LVDS SERDES IP Transmitter and Receiver Design Example

LVDS SERDES IP Dynamic Phase Shift Design Example

Additional LVDS SERDES IP Core References

IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices

Migrating Your ALTLVDS_TX and ALTLVDS_RX IP Cores

LVDS Interface with External PLL Mode

IOPLL IP Signal Interface with LVDS SERDES IP

IOPLL Parameter Values for External PLL Mode

Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode

LVDS Transmitters and Receivers in the Same I/O Bank

Comparison of LVDS SERDES IP Core with Stratix® V SERDES

LVDS SERDES Intel® FPGA IP User Guide Archives

Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

Updated for:
Intel® Quartus® Prime Design Suite 22.1
IP Version 20.0.1

The LVDS SERDES IP configures the serializer/deserializer (SERDES) and dynamic phase alignment (DPA) blocks. The IP also supports LVDS channel placements, legality checks, and LVDS channel-related rule checks.

The LVDS SERDES IP core is available for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices only. If you are migrating designs from Stratix® V, Arria® V, or Cyclone® V devices, you must migrate the ALTLVDS_TX and ALTLVDS_RX IP cores.