Visible to Intel only — GUID: fxd1666032075722
Ixiasoft
Visible to Intel only — GUID: fxd1666032075722
Ixiasoft
5.12.6.7. Watchdog Timers State Machine
If the counter reaches zero, the state changes based on the value of the output response mode setting defined in the rmod bit of the wdt_cr register. If the rmod bit of the wdt_cr register is 0, the output response mode is to generate a system reset request. In this case, the state changes to Assert System Reset Request. In response, the reset manager resets and disables the watchdog timer, and gives software the opportunity to reinitialize the timer.
If the rmod bit of the wdt_cr register is 1, the output response mode is to generate an interrupt. In this case, the state changes to Assert Interrupt and Load Counter with Restart Timeout Value. An interrupt to the processor is generated, and the watchdog counter is reloaded with the restart timeout value. The state then changes to the second Decrement Counter state, and the counter resumes decrementing. If software reads the wdt_eoi register, or writes 0x76 to the wdt_crr register, the state changes from Decrement Counter to Load Counter with Restart Timeout Value. In this state, the watchdog counter gets reloaded with the restart timeout value, and then the state changes back to the first Decrement Counter state. If the counter again reaches zero, the state changes to Assert System Reset Request. In response, the reset manager resets the watchdog timer, and gives software the opportunity to reinitialize the timer.