Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 11/27/2024
Public
Document Table of Contents

5.10.1. SPI Controller Differences Among Altera® SoC Device Families

Table 275.  SPI Controller Differences Among Altera® SoC Device Families

SPI Controller Feature

Cyclone® V SoC,

Arria® V SoC

Arria® 10 SoC

Stratix® 10 SoC

Agilex™ 7

F-Series/I-Series/M-Series SoC

Agilex® 5 E-Series/D-Series SoC

Synopsys* IP Version

3.20a

3.22a

4.00a

4.00a

Number of SPI master cores

2

2

2

2

Number of SPI slave cores

2

2

2

2

Maximum master clock rate

60 MHz

60 MHz

60 MHz

60 MHz

Maximum slave clock rate

50 MHz

50 MHz

33.33 MHz

33.33 MHz

Programmable data frame size

4 to 16 bits

4 to 16 bits

4 to 32 bits

4 to 32 bits

SPI master bit rate clock ratio Fspi_m_clk ≥ 2 × max(Fsclk_out)) Fl4_main_clk ≥ 2 × max(Fsclk_out)
SPI slave bit rate clock ratio Fl4_main_clk ≥ 8 × max(Fsclk_in) Fl4_main_clk ≥ 12 × max(Fsclk_in)

Toggle slave select signal between frames when in SPI mode and SCPH=0?

Yes

Yes

No (slave select signal stays low during data frames transfer)

No (slave select signal stays low during data frames transfer)