Visible to Intel only — GUID: xmq1674177820744
Ixiasoft
Visible to Intel only — GUID: xmq1674177820744
Ixiasoft
5.1.5.4. SMTG Hub Signals and Interface
Signal Name |
Direction |
Description |
---|---|---|
clk_csr_i |
In |
EMAC clock |
rst_n |
In |
EMAC Reset |
gpo1 |
In |
General purpose output from XGMAC core. Software driver sets this bit when time synchronization is required. This bit is cleared by the software when HPS timer value is read over MDIO interface. |
tsc[63:0] |
In |
Timestamp counter (TSC) value, 64-bit bus from HPS timestamp counter. |
tsc_src_clk |
In |
Source clock for TSC. |
ext_ts_trig[1:0] |
In |
External trigger signal for timestamp capture inside EMAC |
ptp_aux_ts_trig[2:0] |
Out |
It is combined with gpo1 trigger pulse with external trigger. ptp_aux_ts_trig = {gpo1_pulse_sync, ext_ts_trig} |
mdc |
In |
MDIO clock |
mdi |
In |
MDIO input |
mdo |
Out |
MDIO Output |
mdo_en |
Out |
MDIO Output Enable |
port_id[4:0] |
In |
MDIO port id for TSC logic (0x15) |
tsc_ctrl_reg_0[31:0] |
In |
Status value of the read-only register-0 |
tsc_ctrl_reg_1[31:0] |
In |
Status value of the read-only register-1 |
tsc_ctrl_reg_2[31:0] |
In |
Status value of the read-only register-2 |
tsc_ctrl_reg_3[31:0] |
In |
Status value of the read-only register-3 |
tsc_cfg_reg0_vld0 |
Out |
Valid signal for configuration register tsc_cfg_reg_0[15:0] |
tsc_cfg_reg0_vld1 |
Out |
Valid signal for configuration register tsc_cfg_reg_0[31:16] |
tsc_cfg_reg1_vld0 |
Out |
Valid signal for configuration register tsc_cfg_reg_1[15:0] |
tsc_cfg_reg1_vld1 |
Out |
Valid signal for configuration register tsc_cfg_reg_1[31:16] |
tsc_cfg_reg_0[31:0] |
Out |
MDIO configuration register-0 |