Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.1.6.11.3. SMTG Hub Integration with the HPS and FPGA

There are three EMACs available in the HPS and each of the EMAC consists of a SMTG hub connected to XGMAC through the MDIO interface. The hub integration with the XGMAC includes the MDIO interface connection and TS capture signal connections to Aux TS[0] capture input of the XGMAC. The XGMAC’s gpo[0] provides a level signal to indicate that the hub needs to generate the TS capture signal (internal and external).

Each hub has two TS capture channels to capture the TS from the HPS system timer and FPGA’s ToD counter. A 65-wire bus is used to connect each time source (HPS system timer and FPGA’s ToD counter) to the hub. It encompasses the 64-bit TS streaming data and associated clock.

The operating system (OS) uses the HPS system timer is a timer/counter for time tracking. You have to enable the HPS system timer to support integration with SMTG hub. It includes the ability to stream 64-bit TS data to the hub which must be gated by the HPS system timer’s clock. A ToD counter in the FPGA fabric can be instantiated as a soft IP and provide 64-bits TS stream to the hub.
Figure 83. Block Diagram of SMTG Integration with the XGMACs, HPS System Timer and a Local ToD Counter in the FPGA

Refer to the following link for the SMTG hub programing guidelines.