Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 11/27/2024
Public
Document Table of Contents

5.9.7.1.3. Slave-Receiver Operation for a Single Byte

When another I2C master device on the bus addresses the I2C controller and is sending data, the I2C controller acts as a slave-receiver and the following steps occur:

  1. The other I2C master device initiates an I2C transfer with an address that matches the I2C controller's slave address in the IC_SAR register.
  2. The I2C controller acknowledges the sent address and recognizes the direction of the transfer to indicate that the I2C controller is acting as a slave-receiver.
  3. I2C controller receives the transmitted byte and places it in the receive buffer.
    Note: If the RX FIFO is completely filled with data when a byte is pushed, then an overflow occurs and the I2C controller continues with subsequent I2C transfers. Because a NACK is not generated, software must recognize the overflow when indicated by the I2C controller (by the R_RX_OVER bit in the IC_INTR_STAT register) and take appropriate actions to recover from lost data. Hence, there is a real time constraint on software to service the RX FIFO before the latter overflow as there is no way to reapply pressure to the remote transmitting master.
  4. I2C controller asserts the RX_FULL interrupt (IC_RAW_INTR_STAT[2] register).

    If the RX_FULL interrupt has been masked, due to setting IC_INTR_MASK[2] register to 0 or setting IC_TX_TL to a value larger than 0, then it is recommended that the CPU does periodic reads of the IC_STATUS register. Reads of the IC_STATUS register, with bit 3 (RFNE) set at 1, must then be treated by software as the equivalent of the RX_FULL interrupt being asserted.

  5. Software may read the byte from the IC_DATA_CMD register (bits 7:0).
  6. The other master device may hold the I2C bus by issuing a RESTART condition or release the bus by issuing a STOP condition.