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Visible to Intel only — GUID: vyp1673393615884
Ixiasoft
5.1.7.19. Programming Guidelines for EST
- Set the current time offset value and time internal left shift fields of the MTL_EST_Control register appropriately. Also, set the enable EST (EEST) and switch to SWOL fields.
- This enables EMAC to own and process the new GCL and switch to the new GCL at the BTR value. If the interrupt is enabled, the EMAC generates an interrupt when it switches to the new GCL.
- Software must address any other interrupts received from the EMAC during the execution of the GCL.
When the software sets the SSWL (Switch to Software Owned List) field in the MTL_EST_Control register, the GCL list is handed-off to the EMAC. When the EMAC has successfully switched to the new GCL list, it resets/clears the SSWL field. EMAC also flips the SWOL field to indicate the new GCL that the software owns. Software is not allowed to write to the GCL and GCL linked registers when the SSWL field is set, because the new GCL might be in use by the EMAC.
To install a new GCL, software must program the GCL it owns (indicated by the SWOL field) as described in Programming the GCL and GCL Linked Registers. Then program the MTL_EST_Control register. Software must ensure that the new BTR is set to an appropriate value to avoid BTR error that may require software intervention.
To avoid transmission overruns, the packet length (frame size) information must be available at all times. Therefore, in the DMA configurations, program the packet length in the first descriptor of every TX frame.
Similarly, in the MTL configuration, you must provide the packet length in the control word. The IPG or EIPG, preamble or SFD overheads are handled by the EMAC. Only the scheduler delays must be included in the EST overhead field as shown in following table.
Speeds |
PTOV (ns) |
CTOV (ns) |
Overhead (in Bytes) |
Per Packet Slot Interval |
Slot Time to be Programmed for n packets |
---|---|---|---|---|---|
2.5 Gbps,1Gpbs, 100 Mbps (GMII) |
10 PTP clock cycles |
3 PTP + 3 TX clock cycles |
Single Port SRAM (SPRAM) Configurations | ||
14 TX + (12+X+Y+Z)Application clock cycles |
(Packet Size + Overhead + IPG +8) * (Time to transmit 1 byte) + 4 TX clock cycles |
n * (Per Packet Slot Interval) + 1 PTPclock cycle | |||
Two Port Asynchronous RAM Configurations |
|||||
10 TX + (12 +X+Y+Z)Application clock cycles |
(Packet Size + Overhead + IPG +8) * (Time to transmit 1 byte) + 4 TX clock cycles |
n * (Per Packet Slot Interval) + 1 PTPclock cycle |
|||
Two Port Synchronous RAM Configurations |
|||||
14 TX + (12+X+Y+Z)Application clock cycles |
(Packet Size + Overhead + IPG +8) * (Time to transmit 1 byte) + 4 TX clock cycles |
n * (Per Packet Slot Interval) + 1 PTPclock cycle |
The value of X, Y, and Z are as follows:
- When TX COE or TSO is selected in the configuration, X is:
- 4 for DW == 32 bits
- 2 when DW != 32 bits
- When TBS or OST is selected in the configuration, Y is
- 4 for DW == 32 bits
- 2 for DW == 64 bits
- When VLAN tag insertion is enabled, Z is
- 2 for DW == 32 bits