Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

9. Power Management

The power manager in the HPS contains logic to power gate SRAM blocks spread across different controllers within the HPS. The power manager also supports the necessary Arm P-channel hardware handshake signals to manage the power of components within the DynamIQ cluster such as the CPU cores and shared L3 cache.

Only power-off operations are supported, and they are done one time as a static option through boot mode user configuration. After power is turned off, the power manager does not support powering back on the CPU cores or L3 cache blocks.

A hardware finite state machine (FSM) is implemented in the power manager to service the MPU boot flow using a configuration that you select. The SDM firmware is responsible for configuring and setting up the DSU, L3 caches, and CPU upon POR. The HPS bootloader is responsible for disabling the SRAM of the unused PSS peripherals.