Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

4.3.4.3.1.6. PMU snapshot Interface for TCU

This interface is for debugging TCU performance monitors. SoC debug unit requests for snapshot of performance monitor counters.

Table 85.  PMU Snapshot signal connection

Signal Name

IO

Connectivity

Description

pmusnapshot_req

I

Connected from CoreSight Debug Engine

PMU (Performance Monitoring Unit) snapshot request. The PMU snapshot occurs on the rising edge of pmusnapshot_req

pmusnapshot_ack

O

Connected to CoreSight Debug Engine

PMU snapshot acknowledge. The

TCU uses this signal to acknowledge that the PMU snapshot has occurred.

As pmusnapshot_req is coming from different clock domain, there is double-flop synchronizer logic added before it gets consumed inside the TCU as shown in the following figure.

Figure 34. The dsync logic for pmusnapshot_req signal

The pmusnapshot_req is expected to be high more than two cycles of SMMU (aclk) clock.