Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

ID 814346
Date 7/19/2024
Public
Document Table of Contents

5.3.6.4.5.1. LUN Interleaving

The NAND controller supports LUN interleaving to achieve the highest possible performance by maximizing the activity on the bus device. For this, when an operation has been started on a particular LUN on a chip, the controller can target some other LUN to start a new operation (that is, LUN interleaving). To achieve this, the host makes use of the multithread support on the command engine in which each triggered command targets a different LUN. For example, if the host sends a Read n Pages command to LUN 0 in thread 0, it is recommended that the host send another command to a different LUN in a different thread, so that the controller can improve the performance of the system.

Figure 132. Thread-LUN Mapping in LUN Interleaving

The interleaving process is essentially handled in the command engine which looks at the next available free LUN to send a command to it. For example, when sending multiple command on different threads but targeting repeated LUNs, the engine handles the sending of the commands until the target LUN is free, but if any of the commands is targeted to a different LUN (a free one), the engine sends this command while waiting until the previous command in the busy LUN finishes. For example, if we have the following sequence of commands targeting a specific LUN: CMD0 to LUN0, CMD1 to LUN0, CMD2 to LUN1, CMD3 to LUN0 all of them in different threads, the engine sends CMD0 first to LUN0, then CMD2 to LUN1 which is free, and then continues sending CMD2 and CMD3 on LUN0 when this gets free.

Operations such as erase, copyback, or data transfer are naturally interleaved by the controller. That is, it is possible to have an erase on one LUN, copyback on the second, and a data transfer into the third for program/read operation. The controller also can handle read/write commands at the same time. The host may, if it chooses, send a data command to read from a particular LUN and may also send a data command to write to a different LUN. The controller also handles any restriction specified by ONFI related to read/write commands sent to the same device with multiple LUNs, but it is recommended that the host should not send parallel read and write data commands on different LUNs at the same time.

Note: It is possible to initiate a program operation when a read operation is ongoing in other LUN if the program_after_read bit in the lun_interleaved_cmd (0x041c) register is set by software.

These are the best scenarios to achieve best performance using interleaving:

  • Only read data commands from a different LUNs.
  • Only write data commands to a different LUNs.

It is recommended that each thread in the command engine binds to individual LUNs of the connected NAND Flash device, to ensure that the threads operate in parallel.

LUN interleaving functionality is based on the following registers:

  • lun_addr_offset (0x0420) register: The controller assumes that each LUN is a separate independent communication thread. The LUN selection is based on the target Flash row address. To address different LUNs in a device, the controller needs to know the targeted chip enable (only one supported) and the row address that is being targeted. This register informs the controller about the boundary index between LUN and block/page addresses. After reset, the default value in this register tells the controller to consider the device connected as a single LUN device.
  • lun_status_cmd (0x0418) register: NAND devices have different ways to read the status of individual LUNs when LUN interleaving operations are in progress. In the ONFI devices, the READ_STATUS_ENHANCED_CMD is used, where the device expects a 0x78 command for status reads for each of the LUNs. Alternatively, the 0xF1/0xF2 commands could be used to read the status of LUN 0/LUN 1. After reset, the controller sets this register to zero (defaulting to ONFI device — command code 0x78). Software can change the value in this register depending on the requirements of the device connected, if necessary.
  • lun_interleaved_cmd (0x041c) register: This register informs the controller what are the valid combinations of command during Multi-LUN operation on the device. The NAND device might have a variety of restrictions as far as LUN interleaved command combinations are concerned, so this register should be configured according to the capabilities of the device connected to the controller. The default values in this register were defined to work on ONFI devices.
  • long_polling (0x0408) and short_polling (0x040c) registers: During LUN interleaving, the ready/busy pin is not monitored by the controller, and instead it reads the status directly from the LUN. To get best performance from the controller, the host should carefully program these registers.
Note: The CMD DMA logic implements device status polling to figure out a device operation completion. Based on single- or multi-LUN operations, single-/multi-plane commands, appropriate read status commands are sent to the device from the controller. In certain rare traffic scenarios, the controller might send 1 or 2 extra status reads to device even if device status received by the controller was a COMPLETED one in the previous status read. This does not affect performance. Even though an extra status read is taking up device bus time, on the other hand, the internal state machine is saving several cycles of RAM-read and internal computation time in such a scenario. Thus overall performance is not affected.